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一、 設計目標要求：

【1】具有“時”、“分”、“秒”計時功能能；

【2】能進行24|12小時計時模式切換；

【3】具有校時和清除功能，能夠對“小時”和“分”進行調整；

【4】具有整點報時功能。在59分51秒、53秒、55秒、57秒發出低音1024Hz信號，在59分59秒發出一次高音2048Hz信號，音響持續1秒鐘，在2048Hz音響結束時刻為整點。

二、 設計原理及效果：

【1】電路原理圖：

【2】設計簡要說明：

本設計在實驗箱上驗證，使用電路模式7，用動態掃描方式顯示，“DS8使能”開關上推；動態位掃描時，時、分、秒之間間隔點亮；

TMODE：12/24進制模式切換，接鍵8；

SCAN：動態掃描時鐘信號，接CLOCK0，跳線選16384Hz；

MINUTE：分校時，接鍵1（單脈沖）；

HOUR：小時時校時，接鍵4（單脈沖）；

EXCHGE：計時/校時切換，接鍵5；

CLK:：時鐘脈沖，接CLOCK2,跳線選1Hz；

RET：清零，接鍵7（單脈沖）；

EN：計數使能，接鍵3；

CLK1024：蜂鳴輸入信號，接CLOCK5,跳線選1024Hz；

SG[6..0]：段選信號，接PIO49到PIO43；

BT[7..0]：位選信號，接PIO41到PIO34；

SPEAKER：蜂鳴輸出信號，接SPEAKER。

【3】實驗效果：

照片描述：晚7點45分07秒（12進制）

照片描述：晚7點45分34秒（24進制）

三、模塊說明：
限于篇幅,程序完整版本請從這里下載：
http://www.zg4o1577.cn/ziliao/file/時鐘daima.rar

【1】60進制模塊——CNT60

LIBRARY IEEE;                                  --------CLK時鐘輸入，RET清零，EN計數使能，

USE IEEE.STD_LOGIC_1164.ALL;                  -------- CQL分或秒的個位輸出，

USE IEEE.STD_LOGIC_UNSIGNED.ALL;            --------CQH分或秒的十位輸出,

ENTITY CNT60 IS                               -------- COUT1進位輸出

PORT (CLK,RST,EN : IN STD_LOGIC;

CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT1 : OUT STD_LOGIC);                      --------向外部的進位

END CNT60;

ARCHITECTURE behav OF CNT60 IS

SIGNAL CQI0: STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL CQI1: STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL COUT0 : STD_LOGIC;                    ------低位向高位的進位

BEGIN 

PROCESS(CLK,RST,EN)                         -------十進制

BEGIN

IF RST='1' THEN CQI0 <=(OTHERS =>'0');

ELSIF CLK'EVENT AND CLK='1' THEN

IF EN ='1' THEN

IF CQI0 <9 THEN CQI0 <=CQI0+1;

ELSE CQI0 <=(OTHERS=>'0');

END IF;

END IF;

IF CQI0 = 9 THEN COUT0 <= '1';

ELSE COUT0<='0';

END IF;

END IF;

END PROCESS;

CQL<=CQI0;

PROCESS(COUT0,RST)                           ------六進制

BEGIN

IF RST='1' THEN CQI1 <=(OTHERS =>'0');

ELSIF COUT0'EVENT AND COUT0='1' THEN

IF CQI1<5 THEN CQI1<=CQI1+1;

ELSE CQI1<=(OTHERS=>'0');

END IF;

IF CQI1=5 AND CQI0=9 THEN COUT1<='1';

ELSE COUT1<='0';

END IF;

END IF;

END PROCESS;

CQH<=CQI1;

END behav;

【2】24|12進制模塊——CNT24 

LIBRARY IEEE;                                      ---------CLK輸入分的進位信號，RET清零，EN計數使能,

USE IEEE.STD_LOGIC_1164.ALL;                      ----------MODE為12和24進制的切換，

USE IEEE.STD_LOGIC_UNSIGNED.ALL;                --------- CQL小時的個位輸出，CQH小時的十位輸出

ENTITY CNT24 IS

PORT (CLK,RST,EN,MODE: IN STD_LOGIC;

CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT24;

ARCHITECTURE behav OF CNT24 IS

SIGNAL CQI0: STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL CQI1: STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL CQI2: STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL CQI3: STD_LOGIC_VECTOR (3 DOWNTO 0);

  BEGIN

P1: PROCESS(CLK,RST,EN)                            --------24進制模式

   BEGIN

     IF RST='1' THEN 

        CQI0 <=(OTHERS =>'0');CQI1 <=(OTHERS =>'0');

        ELSIF CLK'EVENT AND CLK='1' THEN

        IF EN ='1' THEN

         IF CQI1<2 THEN 

          IF CQI0<9 THEN

          CQI0<=CQI0+1;

ELSE CQI0<=(OTHERS=>'0');

CQI1<=CQI1+1;

END IF;

ELSIF CQI0<3 THEN

CQI0<=CQI0+1;

ELSE CQI0<=(OTHERS=>'0');

CQI1<=(OTHERS=>'0');                                                                                                           

   END IF;

       END IF;

      END IF;

     END PROCESS P1;

 P2: PROCESS(CLK,RST,EN)                           ------12進制模式

   BEGIN

     IF RST='1' THEN 

        CQI2 <=(OTHERS =>'0');CQI3 <=(OTHERS =>'0');

        ELSIF CLK'EVENT AND CLK='1' THEN

        IF EN ='1' THEN

         IF CQI3<1 THEN 

          IF CQI2<9 THEN

          CQI2<=CQI2+1;

ELSE CQI2<=(OTHERS=>'0');

CQI3<=CQI3+1;

END IF;

ELSIF CQI2<2 THEN

CQI2<=CQI2+1;

ELSE CQI2<="0001";

CQI3<=(OTHERS=>'0');

END IF;

       END IF;

      END IF;

     END PROCESS P2;  

P3: PROCESS(MODE)                                  ------MODE=’1’為24進制，MODE=’0’為12進制

  BEGIN

  CASE MODE IS

  WHEN '1'=> CQL<=CQI0;CQH<=CQI1;

  WHEN '0'=> CQL<=CQI2;CQH<=CQI3;   

  WHEN OTHERS=>NULL;

  END CASE;

  END PROCESS P3;

END behav;

【3】控制邏輯模塊——CONTROL  

LIBRARY IEEE;                                        -------EXCHGE校時與計時模式控制，

USE IEEE.STD_LOGIC_1164.ALL;                        -------MINUTE手動分校時

USE IEEE.STD_LOGIC_UNSIGNED.ALL;                  -------HOUR手動時校時

ENTITY CONTROL IS                                  -------CY0,CY1分別接受秒和分的進位信號

PORT (MINUTE,HOUR,EXCHGE,CY0,CY1: IN STD_LOGIC;  ------CLK0,CLK1分別控制分和小時的時鐘脈沖

CLK0: OUT STD_LOGIC;

CLK1: OUT STD_LOGIC);

END CONTROL;

ARCHITECTURE behav OF CONTROL IS

SIGNAL A0: STD_LOGIC;

SIGNAL A1: STD_LOGIC;

BEGIN

P1: PROCESS(EXCHGE,MINUTE,HOUR)

   BEGIN

    IF EXCHGE='1' THEN

    A0<=MINUTE;

    A1<=HOUR; 

    END IF;

END PROCESS P1;

P2: PROCESS(EXCHGE,CY0,CY1)                    -------EXCHGE=’1’校時模式，EXCHGE=’0’為計時模式

   BEGIN

     IF EXCHGE='1' THEN

    CLK0<=A0;CLK1<=A1;

    ELSE CLK0<=CY0;CLK1<=CY1;

    END IF;

END PROCESS P2;

END ARCHITECTURE behav;

【4】動態掃描模塊——SCAN_LED 

LIBRARY IEEE;                                             -------SCAN動態掃描時鐘信號

USE IEEE.STD_LOGIC_1164.ALL;                             -------DIN接受時、分、秒數據

USE IEEE.STD_LOGIC_UNSIGNED.ALL;                       -------SG輸出段選信號

ENTITY SCAN_LED IS                                      -------ＢＴ輸出位選信號

 PORT(SCAN : IN STD_LOGIC;

DIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);

SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END;

ARCHITECTURE one OF SCAN_LED IS

 SIGNAL CNT6:STD_LOGIC_VECTOR(2 DOWNTO 0);

 SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0);

 

BEGIN

P1:PROCESS(SCAN)

 BEGIN

 IF SCAN'EVENT AND SCAN='1' THEN

 IF CNT6<5 THEN

 CNT6<=CNT6+1;

 ELSE CNT6<="000";

 END IF;

 END IF;

END PROCESS P1;

P2:PROCESS(CNT6)                                          --------位選

 BEGIN

  CASE CNT6 IS

   WHEN"000"=> BT <="00000001";                             --------時、分、秒之間隔一個數碼管顯示

   WHEN"001"=> BT <="00000010";

   WHEN"010"=> BT <="00001000";

   WHEN"011"=> BT <="00010000";

   WHEN"100"=> BT <="01000000";

   WHEN"101"=> BT <="10000000";

   WHEN OTHERS => NULL;

  END CASE;

END PROCESS P2;

P4: PROCESS(CNT6)

    BEGIN

    CASE CNT6 IS

WHEN"000"=> D <=DIN(3 DOWNTO 0);

WHEN"001"=> D <=DIN(7 DOWNTO 4);

WHEN"010"=> D <=DIN(11 DOWNTO 8);

WHEN"011"=> D <=DIN(15 DOWNTO 12);

WHEN"100"=> D <=DIN(19 DOWNTO 16);

WHEN"101"=> D <=DIN(23 DOWNTO 20);

WHEN OTHERS=>NULL;

    END CASE;

    END PROCESS P4;

P3:PROCESS(D)                                                  -------段選

   BEGIN

 CASE D IS

 WHEN "0000" =>SG<="0111111";WHEN "0001" =>SG<="0000110";

 WHEN "0010" =>SG<="1011011";WHEN "0011" =>SG<="1001111";

 WHEN "0100" =>SG<="1100110";WHEN "0101"=>SG<="1101101";

 WHEN "0110" =>SG<="1111101";WHEN "0111" =>SG<="0000111";

 WHEN "1000" =>SG<="1111111";WHEN "1001" =>SG<="1101111";

 WHEN OTHERS=>NULL;

 END CASE;

END PROCESS P3;

END ARCHITECTURE one;

【5】整點報時模塊——ALARM

LIBRARY IEEE;　　　　　　　　　　　　　　　　　　　　　　------ML輸入分個位，MH輸入分十位

USE IEEE.STD_LOGIC_1164.ALL;                            ------SL輸入秒個位，SH輸入秒十位

USE IEEE.STD_LOGIC_UNSIGNED.ALL;                      ------CLK輸入1024Hz時鐘脈沖

ENTITY ALARM IS                                         ------SPEAKER輸出報時信號

       PORT (ML: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             MH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             SL: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             SH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK: IN STD_LOGIC;

             SPEAKER: OUT STD_LOGIC);

END ALARM;

ARCHITECTURE behav OF ALARM IS

SIGNAL DIV2CLK: STD_LOGIC;

BEGIN

 PROCESS(CLK)

 BEGIN                                               ----------實驗箱的可用時鐘有限，1024Hz作高音信號

   IF CLK'EVENT AND CLK='1' THEN                    -----------1024Hz時鐘脈沖2分頻，產生蜂鳴低音信號

    DIV2CLK<=NOT DIV2CLK;

   END IF;

 END PROCESS;

 PROCESS(MH,ML,SH,SL)

 BEGIN

 IF MH=5 AND ML=9 THEN

  IF SH=5 THEN

   IF (SL=1 OR SL=3 OR SL=5 OR SL=7) THEN            -------51、53、55、57秒輸出低音信號

    SPEAKER<=DIV2CLK;

    ELSIF (SL=9) THEN                                --------59秒輸出高音信號

   SPEAKER<=CLK;

   ELSE SPEAKER<='0';

   END IF;

  ELSE SPEAKER<='0';

  END IF;

 ELSE SPEAKER<='0';

 END IF;

 END PROCESS;

END ARCHITECTURE behav;

【6】頂層實體——CLOCK

LIBRARY IEEE;                                               ------CLK接1Hz時鐘脈沖，

USE IEEE.STD_LOGIC_1164.ALL;                               ------ RET接清零鍵，EN接計數使能鍵，

ENTITY CLOCK IS                                            ------SCAN接CLK0時鐘掃描信號

 PORT(CLK,EN,RST,SCAN,TMODE,EXCHGE:IN STD_LOGIC;       ------TMODE12|24進制切換

      HOUR,MINUTE,CLK1024:IN STD_LOGIC;                  -------EXCHGE計時|校時模式控制

      SPEAKER: OUT STD_LOGIC;                             -------HOUR手動時校時

      SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);             -------MINUTE手動分校時

      BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));             ------CLK1024接1024Hz時鐘脈沖

END ENTITY;                                                 -------SG輸出段選信號

ARCHITECTURE STRUC OF CLOCK IS                           -------BT輸出位選信號

 COMPONENT CNT60                                         ------SPEAKER接蜂鳴器

  PORT (CLK,RST,EN : IN STD_LOGIC;

CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT1 : OUT STD_LOGIC);

 END COMPONENT;

 COMPONENT CNT24 

PORT (CLK,RST,EN,MODE: IN STD_LOGIC;

CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

 END COMPONENT;

 COMPONENT CONTROL

      PORT (MINUTE,HOUR,EXCHGE,CY0,CY1: IN STD_LOGIC;

            CLK0: OUT STD_LOGIC;

CLK1: OUT STD_LOGIC);

 END COMPONENT;

 COMPONENT SCAN_LED

   PORT(SCAN : IN STD_LOGIC;

DIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);

SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

 END COMPONENT;

 COMPONENT ALARM IS

       PORT (ML: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             MH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             SL: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

             SH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK: IN STD_LOGIC;

             SPEAKER: OUT STD_LOGIC);

 END COMPONENT;

     SIGNAL D :STD_LOGIC_VECTOR(23 DOWNTO 0);

     SIGNAL M0,M1,M2,M3 :STD_LOGIC;

     SIGNAL M4,M5,M6,M7 :STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

 u1: CNT60 PORT MAP(CLK=>CLK,RST=>RST,EN=>EN,COUT1=>M0,

                    CQH=>D(7 DOWNTO 4),CQL=>D(3 DOWNTO 0));

 u2: CNT60 PORT MAP(CLK=>M2,RST=>RST,EN=>EN,COUT1=>M1,

                    CQH=>D(15 DOWNTO 12),CQL=>D(11 DOWNTO 8)); 

 u3: CNT24 PORT MAP(CLK=>M3,RST=>RST,EN=>EN,MODE=>TMODE,

                    CQH=>D(23 DOWNTO 20),CQL=>D(19 DOWNTO 16));

 u4: CONTROL PORT MAP(EXCHGE=>EXCHGE,HOUR=>HOUR,MINUTE=>MINUTE,

                      CLK0=>M2,CLK1=>M3,CY0=>M0,CY1=>M1);

 u5: SCAN_LED PORT MAP(SCAN=>SCAN,SG=>SG,BT=>BT,

                      DIN(3 DOWNTO 0)=>D(3 DOWNTO 0),

                      DIN(7 DOWNTO 4)=>D(7 DOWNTO 4),

                      DIN(11 DOWNTO 8)=>D(11 DOWNTO 8),

                      DIN(15 DOWNTO 12)=>D(15 DOWNTO 12),

                      DIN(19 DOWNTO 16)=>D(19 DOWNTO 16), 

                      DIN(23 DOWNTO 20)=>D(23 DOWNTO 20));

 U6: ALARM PORT MAP(ML=>M6,MH=>M7,SL=>M4,SH=>M5,CLK=>CLK1024,

                     SPEAKER=>SPEAKER);

END STRUC;

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