先放實驗要求：













實驗源程序：
module FrameSyn(stateout,dataouten,datawrong,reset,system_clk,mode);
  output reg [3:0] stateout;
  output dataouten,datawrong;
  input [1:0] mode;
  input reset,system_clk;
  wire [1:0] state;
  wire clk,datain,dataout;
  always @(state)
  begin
    case (state)
      2'b00 : stateout = 4'b0001;
      2'b01 : stateout = 4'b0010;
      2'b10 : stateout = 4'b0100;
      2'b11 : stateout = 4'b1000;
    endcase
  end
  FrameSynM FrameSM0(.state(state), .dataout(dataout), .dataouten(dataouten), .reset(reset), .clk(clk), .datain(datain));
  FrameDataCheck FrameDataCheck0(.Reset(reset), .Clock(clk), .DataOut(dataout), .DataOutEn(dataouten), .DataWrong(datawrong));
  FrameTrans FrameTrans0(.Reset(~reset), .Clock100M(system_clk), .Mode(mode), .Clock(clk), .DataIn(datain));
 
endmodule


module FrameSynM(state,dataout,dataouten,reset,clk,datain);
  output reg [1:0] state;
  output reg dataouten;
  output dataout;
  input datain,clk,reset;
  reg [7:0] data_count;
  reg [7:0] frame;
  reg [1:0] matchtimes,mismatchtimes;
 
  assign dataout = datain;
 
  always @(negedge reset or posedge clk)
  begin
    if (!reset)
      begin
        state <= 2'b00;
        frame <= 8'b0000_0000;
        data_count <= 8'b0000_0000;
        matchtimes <= 2'b00;
        mismatchtimes <= 2'b00;
        dataouten <= 0;
      end
    else
      begin
        frame <= {frame[6:0], datain};
        if (state == 2'b00)
          begin

            if (frame == 8'b1001_1011)
              begin
                data_count <=0;
                matchtimes <= matchtimes + 1;
                mismatchtimes <= 2'b00;
              end
            else
              begin
                data_count <= data_count + 1;
                mismatchtimes <= mismatchtimes + 1;
                matchtimes <= 2'b00;
              end
          end
        else
          begin
            data_count <= data_count + 1;
if(data_count==8'b1111_0111)
begin
if(state==2'b10||state==2'b11)
dataouten=1'b0;
end
            if(data_count==8'b1111_1111)
              begin

if(state==2'b10||state==2'b11)
dataouten=1'b1;

                if(frame == 8'b1001_1011)
                  begin
                    matchtimes <= matchtimes + 1;
                    mismatchtimes <= 2'b00;
                  end
                else
                  begin
                    mismatchtimes <= mismatchtimes + 1;
                    matchtimes <= 2'b00;
                  end
              end
          end

        case (state)
          2'b00:
            begin
              if (matchtimes == 1)
                begin
                  state <= 2'b01;
                  dataouten <= 1'b0;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
            end
          2'b01:
            begin
              if (matchtimes == 2)
                begin
                  state <= 2'b10;
                  dataouten <= 1'b1;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
              else if (mismatchtimes == 1)
                begin
                  state <= 2'b00;
                  dataouten <= 1'b0;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
              end
          2'b10:
            begin
              if (mismatchtimes == 1)
                begin
                  state <= 2'b11;
//dataouten <= 1'b1;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
            end
          2'b11:
            begin
              if (matchtimes == 1)
                begin
                  state <= 2'b10;
                  //dataouten <= 1'b1;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
              else if (mismatchtimes == 3)
                begin
                  state <= 2'b00;
                  dataouten <= 1'b0;
                  matchtimes <= 2'b00;
                  mismatchtimes <= 2'b00;
                end
            end
        endcase
      end
  end
endmodule

另產生和檢驗程序老師給出，未放……




測試程序：
`timescale 1ps/1ps
module FrameSynTest;
  reg system_clk,reset;
  reg [1:0] mode;
 
  FrameSyn FrameSyn1(.reset(reset), .system_clk(system_clk), .mode(mode));
 
  initial
  begin
    system_clk=0;
    forever
    #1 system_clk=~system_clk;
  end
 
  initial
  begin
    reset = 0;
    mode = 0;
    #0.5 reset = 1;
    #100000 mode = 2;
    #100000 mode = 3;
    #100000 mode = 2;
  end
 
endmodule


仿真波形：


后記：寫了好長時間……不知道干了點啥。。小時候嚴謹認真的習慣真是太重要了。。。以后培養孩子一定不要這么大大咧咧的，白白浪費掉那么許多好的光陰。。學弟學妹們，如果不幸找到了這篇文章，一定要僅供參考啊……自己寫的才是自己的！！！

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