先編一個JK觸發器帶清0端,項目名稱為dff_JK_111;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Dff_JK_111 IS
PORT (J,K:IN STD_LOGIC;
clk,Rd,Sd: IN std_logic;
Q:out std_logic);
end Dff_JK_111;
ARCHITECTURE behave OF Dff_JK_111 IS
signal S:STD_LOGIC;
signal RS,JK:STD_LOGIC_vector(1 downto 0);
begin
JK<=J&K;
RS<=Rd&Sd;
process(J,K,clk,Rd,Sd,JK,RS)
BEGIN
if RS="11" then
if clk'event and clk='0' Then
case JK is
when "00"=>S<=S;
when "01"=>S<='0';
when "10"=>S<='1';
when "11"=>S<=not S;
end case;
end if;
elsif RS="10" then S<='1';
elsif RS="01" then S<='0';
else Null;
end if;
end process;
Q<= S ;
end behave;