10 ANALOG - TO - DIGTAL CONVERTERS WITH SERIAL CONTROL
引腳圖：
TLC 1549 可有六種工作時(shí)序 ，主要是考慮硬件SPI 接口的速度，因?yàn)橛布䦟?shí)現(xiàn)的SPI必須按字節(jié)讀寫，而1549是10位AD轉(zhuǎn)換器，所以要讀取轉(zhuǎn)換結(jié)果必須按兩字節(jié)既16位操作，故出現(xiàn)了那么多工作模式。當(dāng)采用軟件模擬SPI時(shí)序時(shí)，就不必考慮區(qū)分這6種模式了。
采用GPIO產(chǎn)生控制時(shí)序通常采用10時(shí)鐘周期模式，
10 時(shí)鐘轉(zhuǎn)換 使用CS
10時(shí)鐘不適用 CS
由上圖所示、當(dāng)CS 下降沿和第一個(gè)周期的下降沿讀取高兩位，其余8個(gè)周期用于讀取低8位。從第3個(gè)周期下降沿到第10個(gè)周期下降沿為片內(nèi)采樣周期，然后從第10個(gè)周期下降沿開始后的21us 為轉(zhuǎn)換周期，片選信號(hào)CS 通常采用轉(zhuǎn)換期間無效模式，既在轉(zhuǎn)換過程中把 拉高CS （Figure 6）.這是考慮到芯片的功耗問題，因?yàn)槭鼓苄酒冉剐酒囊喑鲈S多，這一點(diǎn)可直接從1549的datasheet中看出。
從控制時(shí)序圖中可以看出，一個(gè)完整AD 轉(zhuǎn)換周期包括讀取、采樣和量化（轉(zhuǎn)化）三個(gè)過程周期，而且讀取周期和采樣周期部分是重疊的，另外1549轉(zhuǎn)換的一個(gè)重要特點(diǎn)是讀取的數(shù)據(jù)是上次啟動(dòng)AD轉(zhuǎn)換的結(jié)果，這就帶來一個(gè)問題，1549上電后第一次轉(zhuǎn)換如何處理？
顯然芯片上電復(fù)位后，輸出寄存器內(nèi)容并非某次AD轉(zhuǎn)換結(jié)果，可能是一個(gè)隨機(jī)數(shù)或某個(gè)常數(shù)，若直接進(jìn)行轉(zhuǎn)換，首次讀出的數(shù)據(jù)當(dāng)然是錯(cuò)誤的，不過可以采用初始化的方法確保首次讀出的數(shù)據(jù)為第一次啟動(dòng)AD轉(zhuǎn)換的結(jié)果，具體方法是，在上電后首次執(zhí)行一個(gè)初始化函數(shù)ADCClnit(),在函數(shù)中輸出10個(gè)周期脈沖，在第10個(gè)脈沖的下降沿，AD轉(zhuǎn)換被啟動(dòng)，然后等待21us ，最后才進(jìn)入正常的AD轉(zhuǎn)換程序，以后的讀取的數(shù)據(jù)就可以確定是AD轉(zhuǎn)換的真實(shí)值了。
在實(shí)際數(shù)據(jù)采集過程中，
description
The TL1549,TLC1591,and TLC1549M are 10-bit,switched-capacitor,successive-approximation(連續(xù)近似的)analog-to-digital converters.these devices have two digital inputs and 3-state output [chip select (cs低電平有效) ，input-output clock (I/O clock),and data output (DATA OUT)] that provide a three-wire interface to the serial port of a host processor.
The sample-and-hold function is automatic . The converter incorported in these devices features differentil high-impedance reference inputs that facilitate ratiometric conversion,scaling(比例),and isolation（絕緣） of analog ciruitry from logic and supply noise.a switched-capacitor (轉(zhuǎn)換電容器) design allows low-error converson over th full operating free-air temperature range.
The TLC1549C is characterized for operation from 0度 to 70度 。The TLC15491 is characterized for operation from -40 度 to 85度. The TLC 1549M is characterized for operation over the full military temperature range of -55度 to 125度。
detailed description
with chip select (cs) inactive (high),I/O clock is initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes cs active (low ),the cnversion sequence begins with the enabling of I/O clock and the removal of DATA OUT from the high-impedance state.the serial interface then provides the I/O clock sequence to I/O clock and receives the previous conversion result fro DATA OUT .I/O clock receives an input sequence that is between 10 and 16 clock long from the host serial interface .the first ten I/O clocks provide the control timing for sampling the analog input.
there are six basic serial interface timign modes that can be used with the TLC1549. These modes are determined by the speed of I/O clock and the operation of cs shown in Table .these modes are(1) a fast mode with a 10 clock transfer and cs inactive (high ) between transfers,(2)a fast mode with a 10-clock transfer and cs active (low) continuously,(3) a fast mode with an 11-to 16 clock transfer and cs inactive (high) between transfes ,(4) a fast mode with a 16-bit transfer and cs active (low) continuously,(5) a slow mode with an 11 - to 16 -clock transfer and cs inactive (high)between transfers,and(6)a slow mode with a 16 -clock transfer and cs active(low)continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of cs in mode 1,mode 3,and mode 5,withi 21 us from the falling edge of the tenth I/O clock in mode 2 and mode 4,and following the sixteenth clock falling eddge in mode 6.the remaining nine bits are shifted out on the next nine falling edges of I/O clock .Ten bits of data are transmitted to the host serial intrface through DATA OUT.The number of serial clock pulses used also depends on the mode of operation,but a minimum of ten clock pulses is required for conversion o begin.on the tenth clock falling edge,the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I/O clock transfer is more than ten clocks long.
