VHDL除法器宏模塊及編程調用

1.在要調用項目的文件夾創建除法器宏模塊
    按下圖設置和添加宏模塊
































Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity dddd is
Port(a:in std_logic_vector(6 downto 0);
     b:in std_logic_vector(3 downto 0);
   x:out std_logic_vector(6 downto 0);
   y:out std_logic_vector(3 downto 0));
end ;
architecture dd of dddd is
--------定義調用宏模塊
component chufa is
port(numer:in std_logic_vector(6 downto 0);
     denom:in std_logic_vector(3 downto 0);
   quotient:out std_logic_vector(6 downto 0);
     remain:out std_logic_vector(3 downto 0) );
end component;
-----------------結束定義
begin
U:chufa port map(a,b,x,y);  -----調用
end;