d、在CLK第2周期下點(diǎn)擊DIR單元直到該單元變?yōu)楦摺?/div>
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image016.jpg
圖 3-7 激勵(lì)輸入
e、將你的testbench文件存盤，選擇File/Save Waveform或點(diǎn)擊工具欄的存盤圖標(biāo)，接下來HDL Bencher會(huì)提示你設(shè)置你希望仿真的時(shí)鐘周期數(shù)。
f、在End the testbench __cycles after the last input assignment對(duì)話框中輸入8，默認(rèn)值為1。
g、點(diǎn)擊OK.退出HDL Bencher新的testbench波形源文件counter_tbw.tbw自動(dòng)加入到該工程項(xiàng)中。
8、生成預(yù)期的輸出響應(yīng)：
我們進(jìn)行行為仿真以驗(yàn)證計(jì)數(shù)器模塊的功能。
a、在Sources in Project窗口中選擇counter_tbw.tbw文件。
b、在Processes for CurrentSource窗口中點(diǎn)擊+ 符號(hào)展開ModelSim仿真器的層次結(jié)構(gòu)找到并雙擊Simulate BehavioralVHDL Model，此時(shí)ModelSim仿真器自動(dòng)啟動(dòng)。
c、對(duì)于第一次運(yùn)行ModelSim的用戶會(huì)顯示一個(gè)對(duì)話框需要在其中做以下處理：選中Do not show thisdialog again選項(xiàng)，點(diǎn)擊Run ModelSim此對(duì)話框在你重新安裝或重新配置ModelSim之前將不再顯示你的仿真結(jié)果現(xiàn)在顯示在ModelSim的波形窗口(wave window)。
d、點(diǎn)擊Zoom / Zoom Full；點(diǎn)擊Zoom / Zoom in。
e、拖動(dòng)波形窗口下端的滾動(dòng)條至窗口的最左端。
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image018.jpg
圖 3-8 仿真圖
3.3.3 建立頂層原理圖3.3.3.1 生成原理圖符號(hào)1、在Sources in Project窗口中選中計(jì)數(shù)器模塊counter.vhd。
2、在Processes for CurrentSource窗口中，點(diǎn)擊設(shè)計(jì)輸入實(shí)用程序(Design Entry Utilities)之前的“+”符號(hào)然后雙擊創(chuàng)建原理圖符號(hào)(Create SchematicSymbol)經(jīng)過以上步驟，名稱為“counter”的圖形化元件被放入到工程項(xiàng)庫中。
3.3.3.2 創(chuàng)建頂層原理圖1、在工程項(xiàng)導(dǎo)航器(Project Navigator)菜單中，選擇Project/New Source。
2、選擇原理圖(Schematic)為源類型。
3、輸入原理圖名為“top”。
4、先點(diǎn)擊“Next”再點(diǎn)擊“Finish”，此時(shí)原理圖編輯器(ECS)自動(dòng)啟動(dòng)并在其原理圖窗口中打開一張空?qǐng)D。
3.3.3.3 例化VHDL模塊1、在菜單中選擇Add / Symbol或者在工具欄中點(diǎn)擊(Add Symbol)圖標(biāo)。
2、從元件符號(hào)列表(在屏幕右側(cè))中選擇計(jì)數(shù)器counter，注意不要在類別(Categories)窗口中作任何選擇。
3、點(diǎn)擊左鍵可將計(jì)數(shù)器counter放置在光標(biāo)所在的位置出現(xiàn)。
4、按ESC鍵退出添加符號(hào)(Add Symbol)模式。
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image020.jpg
圖3-9 例化VHDL模塊
3.3.3.4 原理圖連線1、首先激活劃線功能通過在菜單中選擇Add/Wire或者在工具欄中點(diǎn)擊 (Add Wire)圖標(biāo)。
2、添加一根懸空線和延展連線，在計(jì)數(shù)器模塊的某一管腳單擊鼠標(biāo)，然后將連線拉伸到需要的長度。再在連線端點(diǎn)處雙擊鼠標(biāo)，給計(jì)數(shù)器模塊的每一管腳添加連線。
3、添加兩個(gè)元件符號(hào)之間的連線，在一個(gè)計(jì)數(shù)器模塊的管腳處單擊鼠標(biāo)，在另一個(gè)計(jì)數(shù)器模塊的對(duì)應(yīng)管腳處雙擊鼠標(biāo)。連接好線后按ESC鍵退出添加連線(Add/Wire)模式。
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image022.jpg
圖3-10 原理圖連線
3.3.3.5 添加輸入輸出管腳標(biāo)記1、在菜單中選擇Add/ (I/O Marker)或在工具欄中點(diǎn)擊(Add I/O Marker)圖標(biāo)，連接好的圖如下。
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image024.jpg
圖3-11 添加輸入輸出管腳
2、連接步驟：首先為clock，reset，ce，load，dir1和dir2添加輸入標(biāo)記，同時(shí)為總線din1(3:0)和din2(3:0)添加輸入標(biāo)記。在工具欄右邊的參數(shù)單選框中選擇輸入(Input)；將鼠標(biāo)移動(dòng)到輸入信號(hào)線的端點(diǎn)，此時(shí)光標(biāo)處顯示出輸入標(biāo)記的圖形；點(diǎn)擊鼠標(biāo)左鍵，輸入標(biāo)記會(huì)將網(wǎng)絡(luò)名或總線名包含在標(biāo)記圖形的內(nèi)部。
3、按如下步驟為count總線添加雙向信號(hào)標(biāo)記。在工具欄右邊的參數(shù)單選框中選擇雙向(Bidirectional)；將鼠標(biāo)移動(dòng)到輸出信號(hào)線的端點(diǎn)，此時(shí)光標(biāo)處顯示出雙向信號(hào)標(biāo)記的圖形；點(diǎn)擊鼠標(biāo)左鍵。
4、在菜單中選擇File/Save，保存原理圖,退出原理圖編輯器(ECS)。
3.3.4 綜合3.3.4.1 Synthesize綜合當(dāng)你編寫程序后，并把頂層原理圖連接好以后，就可以綜合了。選中你的頂層文件，雙擊Synthesize-SynplifyPro。
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image026.jpg
圖3-12 綜合
如果出現(xiàn)上圖的小勾，表示綜合沒有問題。你可以雙擊View RTL Schematic來查看綜合后的RTL原理圖。
3.3.4.2 定義輸入輸出管腳約束選中頂層文件，雙擊下圖中的Assign Package Pins，該操作會(huì)提示系統(tǒng)將生成一個(gè).ucf文件，選擇是，系統(tǒng)將自動(dòng)啟動(dòng)Xilinx Pace。
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圖3-13 分配引腳
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圖3-14 Xilinx Pace
現(xiàn)在就可以在LOC欄寫上管腳名，定義I/O電平類型，輸出電流大小等，需要注意的是一些I/O是有特殊用處的，不能胡亂分配。定義完后保存退出。
3.3.5 布局布線雙擊Implement Design，會(huì)依次執(zhí)行Translate，Map，Place&Route。
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圖3-15 設(shè)計(jì)實(shí)現(xiàn)
3.3.6 下載及硬件仿真選中頂層文件，雙擊運(yùn)行Generate ProgrammingFile，運(yùn)行后生成相應(yīng)的（.Bit）下載文件。該文件將下載到芯片中實(shí)現(xiàn)設(shè)計(jì)。
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圖3-16 生成下載文件
再雙擊上圖Configure Device。運(yùn)行后跳出下載界面，選擇主從下載文式（Slave Serial Mode），點(diǎn)擊完成。
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圖3-17 下載方式
右鍵點(diǎn)擊元件，點(diǎn)擊Program，選擇相應(yīng)的BIT文件開始下載。
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圖3-18 下載位文件
成功下載后就可以在FPGA板子上運(yùn)行和測(cè)試了。
第四章 數(shù)字秒表的設(shè)計(jì)與實(shí)現(xiàn)一、 項(xiàng)目任務(wù)與設(shè)計(jì)思路
1、實(shí)驗(yàn)項(xiàng)目
數(shù)字秒表的設(shè)計(jì)
2、實(shí)驗(yàn)指標(biāo)
晶振輸入信號(hào)：50MHZ時(shí)鐘信號(hào)
計(jì)時(shí)范圍范圍為：00：00：00到59：59：99
按鈕開關(guān)：start/stop,split/reset
在秒表已經(jīng)被復(fù)位的情況下，按下start/stop鍵，秒表開始計(jì)時(shí)。在秒表正常運(yùn)行的情況下，如果按下start/stop鍵，則秒表暫停計(jì)時(shí)；再次按下該鍵，秒表繼續(xù)計(jì)時(shí)。在秒表正常運(yùn)行情況下，如果按下split/reset鍵，顯示停止在按鍵時(shí)間，但秒表仍然計(jì)時(shí)，再次按下該鍵，秒表恢復(fù)正常顯示。在秒表暫停計(jì)時(shí)情況下，按下split/reset鍵，秒表復(fù)位歸零。
顯示工作方式：用六位BCD七段數(shù)碼管顯示讀數(shù)。
3、實(shí)驗(yàn)思路
根據(jù)實(shí)驗(yàn)指標(biāo)，將電路設(shè)計(jì)分成6個(gè)模塊：分頻器，計(jì)數(shù)器，鎖存器，掃描顯示控制，按鍵消陡，控制電路
二、 基于VHDL方法的設(shè)計(jì)方案
1、系統(tǒng)需求和解決方案計(jì)劃
在項(xiàng)目開始設(shè)計(jì)時(shí)，首先要確定系統(tǒng)的需求并發(fā)展出一個(gè)針對(duì)這些需求的計(jì)劃。
晶振 本設(shè)計(jì)所用為 50MHz的晶振信號(hào)。
分頻器
對(duì)晶體振蕩器產(chǎn)生的時(shí)鐘信號(hào)進(jìn)行分頻，產(chǎn)生時(shí)間基準(zhǔn)信號(hào)。本設(shè)計(jì)中將50MHz的信號(hào)分頻成1KHz的基準(zhǔn)頻率
計(jì)數(shù)器
對(duì)時(shí)間基準(zhǔn)脈沖進(jìn)行計(jì)數(shù)，完成計(jì)時(shí)功能。本設(shè)計(jì)中采用六進(jìn)制與十進(jìn)制計(jì)數(shù)器級(jí)聯(lián)的形式。
數(shù)據(jù)鎖存器
鎖存數(shù)據(jù)使顯示保持暫停
控制器
控制計(jì)數(shù)器的運(yùn)行、停止以及復(fù)位、產(chǎn)生鎖存器的使能信號(hào)。本設(shè)計(jì)中為一個(gè)moore機(jī)，可以讓狀態(tài)編碼為相應(yīng)的輸出以方便程序編寫。
掃描顯示的控制電路
包括掃描計(jì)數(shù)器、數(shù)據(jù)選擇器、3*8譯碼器和7段譯碼器，控制8個(gè)數(shù)碼管
以掃描方式顯示計(jì)時(shí)結(jié)果。本設(shè)計(jì)中一個(gè)八進(jìn)制的計(jì)數(shù)器產(chǎn)生的掃描信號(hào)同時(shí)
完成從鎖存器送來的信號(hào)的選擇以及LED數(shù)碼管的選擇。
按鍵消抖電路
消除按鍵輸入信號(hào)抖動(dòng)的影響，輸出單脈沖。本設(shè)計(jì)中采用軟件延時(shí)的消抖方法。
2、設(shè)計(jì)方框圖
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四、系統(tǒng)電路設(shè)計(jì)
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五、系統(tǒng)單元模塊設(shè)計(jì)
1、分頻器模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image046.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity fre_div is
port(clk_50MHz:instd_logic;
clk_1KHz:outstd_logic
);
end fre_div;
architecture Behavioral of fre_div is
signal counter:std_logic_vector(15downto 0);
begin
process(clk_50MHz)
begin
ifrising_edge(clk_50MHz) then
ifcounter=49999 then
counter<=(others=>'0');
else
counter<=counter+1;
end if;
end if;
end process;
--clk_1KHz <=counter(15);
clk_1KHz <='1' when counter=49999 else '0';
end Behavioral;
2、計(jì)數(shù)器模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image048.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity jishuqi is
port( count_en: in std_logic;
count_clr: in std_logic;
clk: in std_logic;
D, D0,D1,D3,D4,D6,D7 : outstd_logic_vector(3 downto 0)
);
end jishuqi;
architecture Behavioral of jishuqi is
COMPONENTm10jishu
PORT(
clk : INstd_logic;
count_en : INstd_logic;
count_clr :IN std_logic;
carry_out :OUT std_logic;
data : OUTstd_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENTm6jishu
PORT(
clk : INstd_logic;
count_en : INstd_logic;
count_clr :IN std_logic;
carry_out :OUT std_logic;
data : OUTstd_logic_vector(3 downto 0)
);
END COMPONENT;
signal c0,c1,c2,c3,c4,c5 : std_logic;
begin
Inst_m10jishu0:m10jishu PORT MAP(
clk =>clk,
count_en=> count_en,
count_clr=> count_clr,
carry_out=> c0,
data => D
);
Inst_m10jishu1:m10jishu PORT MAP(
clk =>clk,
count_en=> c0,
count_clr=> count_clr,
carry_out=> c1,
data => D0
);
Inst_m10jishu2:m10jishu PORT MAP(
clk =>clk,
count_en=> c1,
count_clr=> count_clr,
carry_out=> c2,
data => D1
);
Inst_m10jishu3:m10jishu PORT MAP(
clk => clk,
count_en=> c2,
count_clr=> count_clr,
carry_out=> c3,
data => D3
);
Inst_m6jishu1:m6jishu PORT MAP(
clk =>clk,
count_en=> c3,
count_clr=> count_clr,
carry_out=> c4,
data => D4
);
Inst_m10jishu4:m10jishu PORT MAP(
clk =>clk,
count_en=> c4,
count_clr=> count_clr,
carry_out=> c5,
data => D6
);
Inst_m6jishu2:m6jishu PORT MAP(
clk =>clk,
count_en=> c5,
count_clr=> count_clr,
carry_out=> open,
data => D7
);
end Behavioral;
2.1模十計(jì)數(shù)器模塊：
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image050.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entity m10jishu is
port(clk: in std_logic;
count_en: in std_logic;
count_clr: in std_logic;
carry_out: out std_logic;
data: out std_logic_vector(3 downto 0)
);
end m10jishu;
architecture Behavioral ofm10jishu is
signal c_state,n_state:std_logic_vector(3 downto 0):="0000";
begin
label_1:process(count_en,c_state)
begin
if count_en ='1' then
ifc_state="1001" then
n_state<="0000";
--carry_out <= '1' ;
else n_state<=c_state+1;
-- carry_out <='0';
end if;
else n_state<=c_state;
end if;
end process;
label_2:process(clk,count_clr)
begin
if count_clr='1' then
c_state<="0000";
elsif rising_edge(clk) then
c_state<=n_state;
end if;
end process;
carry_out <= '1' when c_state="1001" andcount_en='1' else '0';
data <= c_state;
end Behavioral;
2.2模六計(jì)數(shù)器：
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image052.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity m6jishu is
port(clk: in std_logic;
count_en: in std_logic;
count_clr: in std_logic;
carry_out: out std_logic;
data: out std_logic_vector(3downto 0)
);
end m6jishu;
architecture Behavioral of m6jishu is
signal c_state,n_state: std_logic_vector(3 downto 0):="0000";
begin
label_1:process(count_en,c_state)
begin
if count_en='1' then
if c_state="0101" then
n_state <= "0000";
-- carry_out <= '1';
else n_state<=c_state+1;
--carry_out <= '0';
end if;
else n_state<=c_state;
end if;
end process;
label_2:process(clk,count_clr)
begin
if count_clr='1' then
c_state<="0000";
elsif rising_edge(clk) then
c_state<=n_state;
end if;
end process;
carry_out <= '1' whenc_state="0101" and count_en='1' else '0';
data <= c_state;
end Behavioral;
3、掃描顯示控制電路
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file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image056.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity smxs_control is
port( clk_1KHz : in std_logic;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7: in std_logic_vector(3 downto 0);
DIG: out std_logic_vector(7 downto 0);
SEG: out std_logic_vector(6 downto 0)
);
end smxs_control;
architecture Behavioral of smxs_control is
COMPONENTsaomiaojishu
PORT(
clk: IN std_logic;
data: OUT std_logic_vector(2 downto 0)
);
ENDCOMPONENT;
COMPONENTyima38
PORT(
S: IN std_logic_vector(2 downto 0);
DIG: OUT std_logic_vector(7 downto 0)
);
ENDCOMPONENT;
COMPONENTdselect
PORT(
Q0: IN std_logic_vector(3 downto 0);
Q1: IN std_logic_vector(3 downto 0);
Q2: IN std_logic_vector(3 downto 0);
Q3: IN std_logic_vector(3 downto 0);
Q4: IN std_logic_vector(3 downto 0);
Q5: IN std_logic_vector(3 downto 0);
Q6: IN std_logic_vector(3 downto 0);
Q7: IN std_logic_vector(3 downto 0);
S: IN std_logic_vector(2 downto 0);
BCD: OUT std_logic_vector(3 downto 0)
);
ENDCOMPONENT;
COMPONENTyima7
PORT(
BCD: IN std_logic_vector(3 downto 0);
SEG: OUT std_logic_vector(6 downto 0)
);
ENDCOMPONENT;
signal s : std_logic_vector(2downto 0);
signal bcd : std_logic_vector(3 downto 0);
begin
Inst_saomiaojishu:saomiaojishu PORT MAP(
clk=> clk_1KHz,
data=> s
);
Inst_yima38:yima38 PORT MAP(
S=> s,
DIG=> DIG
);
Inst_dselect:dselect PORT MAP(
Q0=> Q0,
Q1=> Q1,
Q2=> Q2,
Q3=> Q3,
Q4=> Q4,
Q5=> Q5,
Q6=> Q6,
Q7=> Q7,
S=> s,
BCD=> bcd
);
Inst_yima7:yima7 PORT MAP(
BCD=> bcd,
SEG=> SEG
);
end Behavioral;
3.1掃描計(jì)數(shù)模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image058.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entity saomiaojishu is
port(clk: in std_logic;
data: out std_logic_vector(2 downto 0)
);
end saomiaojishu;
architecture Behavioral ofsaomiaojishu is
signal c_state,n_state: std_logic_vector(2 downto0):="000";
begin
label_1:process(c_state)
begin
if c_state="111" then
n_state <= "000";
else n_state<=c_state+1;
end if;
end process;
label_2:process(clk)
begin
if rising_edge(clk) then
c_state<=n_state;
end if;
end process;
data <= c_state;
end Behavioral;
3.2數(shù)據(jù)選擇模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image060.jpg
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entitydselect is
port(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 : instd_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0) ;
BCD : out std_logic_vector(3 downto0)
);
enddselect;
architectureBehavioral of dselect is
begin
process(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,S)
begin
if S = "000" then
BCD <= Q0;
elsif S = "001" then
BCD <= Q1;
elsif S = "010" then
BCD <= Q2;
elsif S = "011" then
BCD <= Q3;
elsif S = "100" then
BCD <= Q4;
elsif S = "101" then
BCD <= Q5;
elsif S = "110" then
BCD <= Q6;
elsif S = "111" then
BCD <= Q7;
else BCD <= "0000";
end if;
endprocess;
endBehavioral;
3.33*8譯碼模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image062.jpg
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entityyima38 is
port( S:in std_logic_vector(2 downto 0) ;
DIG:out std_logic_vector(7 downto 0)
);
endyima38;
architectureBehavioral of yima38 is
begin
WITH S SELECT
DIG <= "11111110" when"000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
endBehavioral;
3.4、七段譯碼器模塊：
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image064.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity yima7 is
port( BCD : in std_logic_vector(3 downto0);
SEG: out std_logic_vector(6 downto 0)
);
end yima7;
architecture Behavioral of yima7 is
begin
process(BCD)
begin
caseBCD is
when "0000" => SEG <= "0000001";
when"0001" => SEG <= "1001111" ;
when"0010" => SEG <= "0010010" ;
when"0011" => SEG <= "0000110" ;
when"0100" => SEG <= "1001100" ;
when"0101" => SEG <= "0100100" ;
when"0110" => SEG <= "0100000" ;
when"0111" => SEG <= "0001111" ;
when"1000" => SEG <= "0000000" ;
when"1001" => SEG <= "0000100" ;
when"1111" => SEG <= "1111110" ;
whenothers => SEG <= "1111111" ;
endcase;
endprocess;
end Behavioral;
4、按鍵消抖模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image066.jpg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;-- Uncomment the followinglibrary declaration if using
entity key_debounce is
Port ( clk :in STD_LOGIC;
key_in :in STD_LOGIC;
key_out :out STD_LOGIC);
end key_debounce;
architecture Behavioral of key_debounce is
signal k1,k2 :STD_LOGIC;
signal cnt : STD_LOGIC_VECTOR(1 downto 0);
begin
process(clk,key_in)
begin
if clk'event andclk = '0' then
if cnt = 3 then
k1 <='1';
else
k1 <= '0';
cnt <= cnt+ 1;
end if;
k2 <= k1;
end if;
if key_in = '0'then
cnt <="00";
end if;
end process;
key_out <= not k1and k2;
end Behavioral;
4、鎖存器模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image068.jpg
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entitylatch is
port( D0,D1,D2,D3,D4,D5,D6,D7: in std_logic_vector(3 downto 0);
latch_en : in std_logic;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 : outstd_logic_vector(3 downto 0)
);
endlatch;
architectureBehavioral of latch is
begin
lable:process(D0,D1,D2,D3,D4,D5,D6,D7,latch_en)
begin
if latch_en = '1' then
Q0<= D0;
Q1<= D1;
Q2<= D2;
Q3<= D3;
Q4<= D4;
Q5<= D5;
Q6<= D6;
Q7<= D7;
endif;
end process;
endBehavioral;
5、控制電路模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image070.jpg
libraryIEEE;
use IEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entitycontrol is
port(clk : in std_logic;
start : in std_logic;
reset : in std_logic;
count_clr : out std_logic;
count_en : out std_logic;
latch_en : out std_logic
);
endcontrol;
architectureBehavioral of control is
signalsr: std_logic_vector(1 downto 0);
signalccl:std_logic_vector(2 downto 0):="111";
signalccl_out : std_logic_vector(2 downto 0) ;
begin
sr<= start & reset;
lable_1:process(sr,ccl)
begin
case ccl is
when "111" =>
if sr="10" then ccl_out <= "011";
else ccl_out <= "111";
end if;
when "011" =>
if sr="01" then ccl_out <= "010";
elsif sr="10" then ccl_out <= "001";
else ccl_out <= "011";
end if;
when "001" =>
if sr="01" then ccl_out <= "111";
elsif sr="10" then ccl_out <= "011";
else ccl_out <= "001";
end if;
when "010" =>
if sr="01" then ccl_out <= "011";
else ccl_out <= "010";
end if;
when others => ccl_out <="111";
end case;
end process;
lable_2: process(clk)
begin
if rising_edge(clk) then
ccl <= ccl_out;
end if;
end process;
count_clr<= ccl(2);
count_en <= ccl(1);
latch_en <= ccl(0);
endBehavioral;
6、數(shù)字秒表頂層連接模塊
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image071.jpg
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
entitymiaobiao_top is
port(key1,key2 : in std_logic;
clk_50MHz : in std_logic;
DIG : out std_logic_vector(7 downto 0);
SEG : out std_logic_vector(6 downto 0)
);
end miaobiao_top;
architectureBehavioral of miaobiao_top is
signalk1,k2,CLK,clr,cen,len : std_logic;
signaldd0,dd1,dd3,dd4,dd6,dd7 : std_logic_vector(3 downto 0);
signalqq1,qq2,qq3,qq4,qq5,qq6,qq7,qq0 : std_logic_vector(3 downto 0);
COMPONENT key_debounce1
PORT(
clk : IN std_logic;
key_in : IN std_logic;
key_out : OUT std_logic
);
END COMPONENT;
COMPONENT key_debounce
PORT(
clk : IN std_logic;
key_in : IN std_logic;
key_out : OUT std_logic
);
END COMPONENT;
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
reset : IN std_logic;
count_clr : OUT std_logic;
count_en : OUT std_logic;
latch_en : OUT std_logic
);
END COMPONENT;
COMPONENT fre_div
PORT(
clk_50MHz : IN std_logic;
clk_1KHz : OUT std_logic
);
END COMPONENT;
COMPONENT jishuqi
PORT(
count_en : IN std_logic;
count_clr : IN std_logic;
clk : IN std_logic;
D : OUT std_logic_vector(3 downto 0);
D0 : OUT std_logic_vector(3 downto 0);
D1 : OUT std_logic_vector(3 downto 0);
D3 : OUT std_logic_vector(3 downto 0);
D4 : OUT std_logic_vector(3 downto 0);
D6 : OUT std_logic_vector(3 downto 0);
D7 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT latch
PORT(
D0 :IN std_logic_vector(3 downto 0);
D1 : IN std_logic_vector(3 downto 0);
D2 : IN std_logic_vector(3 downto 0);
D3 : IN std_logic_vector(3 downto 0);
D4 : IN std_logic_vector(3 downto 0);
D5 : IN std_logic_vector(3 downto 0);
D6 : IN std_logic_vector(3 downto 0);
D7 : IN std_logic_vector(3 downto 0);
latch_en : IN std_logic;
Q0 : OUT std_logic_vector(3 downto 0);
Q1 : OUT std_logic_vector(3 downto 0);
Q2 : OUT std_logic_vector(3 downto 0);
Q3 : OUT std_logic_vector(3 downto 0);
Q4 : OUT std_logic_vector(3 downto 0);
Q5 : OUT std_logic_vector(3 downto 0);
Q6 : OUT std_logic_vector(3 downto 0);
Q7 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT smxs_control
PORT(
clk_1KHz : IN std_logic;
Q0 : IN std_logic_vector(3 downto 0);
Q1 : IN std_logic_vector(3 downto 0);
Q2 : IN std_logic_vector(3 downto 0);
Q3 : IN std_logic_vector(3 downto 0);
Q4 : IN std_logic_vector(3 downto 0);
Q5 : IN std_logic_vector(3 downto 0);
Q6 : IN std_logic_vector(3 downto 0);
Q7 : IN std_logic_vector(3 downto 0);
DIG : OUT std_logic_vector(7 downto 0);
SEG : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
begin
Inst_key_debounce1: key_debounce PORT MAP(
clk => CLK,
key_in => key1,
key_out=> k1
);
Inst_key_debounce2: key_debounce PORT MAP(
clk => CLK,
key_in => key2,
key_out => k2
);
Inst_control: control PORT MAP(
clk => CLK ,
start => k1,
reset => k2,
count_clr => clr,
count_en => cen,
latch_en => len
);
Inst_fre_div: fre_div PORT MAP(
clk_50MHz => clk_50MHz,
clk_1KHz => CLK
);
Inst_jishuqi: jishuqi PORT MAP(
count_en => cen,
count_clr => clr,
clk => CLK,
D => open,
D0 => dd0,
D1 => dd1,
D3 => dd3,
D4 => dd4,
D6 => dd6,
D7 => dd7
);
Inst_latch: latch PORT MAP(
D0 => dd0,
D1 => dd1,
D2 => "1111",
D3 => dd3,
D4 => dd4,
D5 => "1111",
D6 => dd6,
D7 => dd7,
latch_en => len,
Q0 => qq0,
Q1 => qq1,
Q2 => qq2,
Q3 => qq3,
Q4 => qq4,
Q5 => qq5,
Q6 => qq6,
Q7 => qq7
);
Inst_smxs_control: smxs_control PORT MAP(
clk_1KHz => CLK,
Q0 => qq0,
Q1 => qq1,
Q2 => qq2,
Q3 => qq3,
Q4 => qq4,
Q5 => qq5,
Q6 => qq6,
Q7 => qq7,
DIG => DIG,
SEG => SEG
);
endBehavioral;
三、 系統(tǒng)硬件實(shí)現(xiàn)與調(diào)試
管腳分配：
NET "DIG[0]" LOC =P81;
NET "DIG[1]" LOC =P85;
NET "DIG[2]" LOC =P83;
NET "DIG[3]" LOC =P82;
NET "DIG[4]" LOC =P43;
NET "DIG[5]" LOC =P74;
NET "DIG[6]" LOC =P59;
NET "DIG[7]" LOC =P51;
NET "clk_50MHz" LOC= P128;
NET "key1" LOC =P47;
NET "key2" LOC = P48;
NET "SEG[0]" LOC =P53;
NET "SEG[1]" LOC =P54;
NET "SEG[2]" LOC =P77;
NET "SEG[3]" LOC =P76;
NET "SEG[4]" LOC =P58;
NET "SEG[5]" LOC =P75;
NET "SEG[6]" LOC =P52;
第五章 實(shí)驗(yàn)總結(jié)及心得體會(huì)1、這次實(shí)驗(yàn)是利用VHDL語言完成基于FPGA的數(shù)字秒表的設(shè)計(jì)與實(shí)現(xiàn)。通過實(shí)驗(yàn)掌握了設(shè)計(jì)方案以及各模塊的設(shè)計(jì)過程及其實(shí)現(xiàn)的功能，及對(duì)設(shè)計(jì)中遇到的問題分析和解決方法；學(xué)會(huì)了利用ISE和ModelSim對(duì)設(shè)計(jì)進(jìn)行了仿真，分析，綜合還熟悉了Xilinx ISE 和ModelSim軟件的用法和VHDL 的編程環(huán)境，，并最終下載到Spartan3E系列芯片中，實(shí)現(xiàn)了對(duì)數(shù)字秒表的測(cè)量。
2、通過《電子技術(shù)綜合實(shí)驗(yàn)》課程的學(xué)習(xí)，我第一次接觸到VHDL語言，并學(xué)會(huì)了用VHDL語言設(shè)計(jì)簡(jiǎn)單的電路模塊。使我對(duì)系統(tǒng)設(shè)計(jì)原理、主要性能參數(shù)的選擇原則、單元電路和系統(tǒng)電路設(shè)計(jì)方法及仿真技術(shù)、測(cè)試方案擬定及調(diào)測(cè)技術(shù)有了初步了解；初步掌握電子技術(shù)中應(yīng)用開發(fā)的一般流程，初步建立起有關(guān)系統(tǒng)設(shè)計(jì)的基本概念，掌握其基本設(shè)計(jì)方法，為將來走出校園從事電子技術(shù)應(yīng)用和研究工作打下基礎(chǔ)
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