vhdl測量頻率并用數碼管顯示程序

ID:149351 · 發表于 2016-11-21 22:10

資料下載：

adc.rar (3.92 MB, 下載次數: 18)

module adc (
clk,rst_n,clk_beep,
eoc,
start,oe,ale,adda,
data,data_r,led,
key_smg_n,
smg1,smg2,smg3,smg5,smg6,
led1,led2,led3,beep
);
input key_smg_n;
output reg beep; // 蜂鳴器
input clk_beep; //蜂鳴器時鐘
output reg led2; //整形后得到的脈沖
output reg led1;//量程進位需要的小數點，用燈來控制
output reg led3; //超量程警告
output reg[3:0]smg1; //smg1,smg2,smg3 數碼管顯示測得頻率具有自動轉換量程的功能
output reg[3:0]smg2;
output reg[3:0]smg3;
output reg[3:0]smg5; //smg5 smg6 數碼管顯示占空比
output reg[3:0]smg6;
output reg start,oe,ale,adda;
input eoc,clk,rst_n;
input [7:0] data;
output reg led;
//===========================================================================================================
//ADC初始化，用來進行模數轉化
//===========================================================================================================
output reg [7:0] data_r;
reg[4:0] CS,NS;
parameter IDLE = 5'b00001,START_H = 5'b00010,START_L = 5'b00100,CHECK_END = 5'b01000,GET_DATA = 5'b10000;
always @ (posedge clk)
case(CS)
IDLE: NS = START_H;
START_H: NS=START_L;
START_L: NS=CHECK_END;
CHECK_END: begin if(eoc==1'b1) NS=GET_DATA;
else NS = CHECK_END;
end
GET_DATA:NS=IDLE;
default : NS = IDLE;
endcase
always @ (posedge clk)
if(!rst_n) CS<=IDLE;
else CS<=NS;
always @(posedge clk)
case(NS)
IDLE:begin oe<=0; start <=0; ale <= 0; adda<=1; end
START_H: begin oe<=0; start<=1;ale<=1;adda<=1; end
START_L: begin oe<=0; start<=0;ale<=1; end
CHECK_END: begin oe <= 0; start<=0; ale<=0;end
GET_DATA: begin oe<=1;data_r<=data;start<=0;ale<=0;end
endcase
//****************************************************************************************************
//****************************************************************************************************
//==========================================
//整形模塊，無論是方波還是三角波或者正選波，
//都能變為高低脈沖
//=======================================
always @ (posedge clk)
if(!rst_n) led <= 1'b0;
else if(data_r<=8'd127) led <= 1'b0;
else led<=1'b1;
//********************************************************************************
/*===================================================================================================
測量頻率模塊
利用往后打一拍的原理，來控制信號
====================================================================================================*/
parameter CLK_1HZ = 25'd3000000;
reg[24:0] delay_cnt1;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) delay_cnt1 <= 1'b0;
else if(delay_cnt1<=CLK_1HZ)
delay_cnt1<=delay_cnt1+1'b1;
else
delay_cnt1<= 1'b0;
end
wire delay_1ss = (delay_cnt1==CLK_1HZ)?1'b1:1'b0; // 利用該信號清零
wire delay_1s = (delay_cnt1==CLK_1HZ-1'b1)?1'b1:1'b0;// 利用該信號存儲信號
reg [24:0] cnt_n;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) cnt_n <= 1'b0;
else if(delay_1ss == 1'b0)begin
if(count_an == 1'b1) //檢測是否有下降沿
cnt_n <= cnt_n+1'b1;
else cnt_n<=cnt_n;
end
else cnt_n <= 1'b0;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin smg1<=1'b0;smg2<=1'b0;smg3<=1'b0;smg5<=1'b0;smg6<=1'b0;led1<=1'b0;led2<=1'b0;led3<=1'b0; end
else if(key_smg_n == 1)
begin smg5<=1'b0;
if(delay_1s == 1'b1) begin
if(cnt_n < 14'd999) begin //低量程 0~999hz
led1<=1'b0;
led3<=1'b0;
smg6 <= cnt_n % 4'd10;
smg1 <= cnt_n / 4'd10 %4'd10;
smg2 <= cnt_n /7'd100 %4'd10;
smg3 <= cnt_n /10'd1000 %4'd10;
end
else if(cnt_n<=15'd3000)begin // 高量程 1000~3000hz
led1<=1'b1;
led3<=1'b0;
smg1 <= cnt_n / 4'd10 % 4'd10;
smg2 <= cnt_n / 7'd100 %4'd10;
smg3 <= cnt_n /10'd1000 %4'd10;
smg6 <= cnt_n % 4'd10;
end
else begin // 超量程蜂鳴器響，燈亮
beep <= clk_beep;
led3<=1'b1;
end
end
end
else begin
smg1<=1'b0;smg2<=1'b0;smg3<=1'b0;
if(delay_1s) begin
smg5 <= (cnt_up *7'd100 / cnt_down) % 4'd10 ;
smg6 <= (cnt_up *7'd100 / cnt_down) / 4'd10;
end
end
end
//**************************************************************************************************
/*==================================================================================================
占空比測量信號
待測脈沖高電平的時候用一個計數器計數
低電平的時候用另一個計數器計數
高電平計數與總共的比值。
====================================================================================================*/
reg [31:0] cnt_up;
reg [31:0] cnt_down;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin cnt_up<=1'b0; cnt_down<=1'b0; end
else if(delay_1ss == 1'b0) begin
if(led == 1'b1) begin cnt_up<=cnt_up+1'b1; cnt_down<=cnt_down+1'b1; end
else begin cnt_down <= cnt_down + 1'b1; cnt_up<=cnt_up; end
end
else begin cnt_up <= 1'b0; cnt_down <= 1'b0; end
end
/*
always@(posedge clk or negedge rst_n) begin
if(!rst_n)begin smg5<=1'b0;smg6<=1'b0; end
else if(key_smg_n == 0) begin
if(delay_1s) begin
smg5 <= (cnt_up *7'd100 /(cnt_up+cnt_down)) % 4'd10 ;
smg6 <= (cnt_up *7'd100 /(cnt_up+cnt_down)) / 4'd10;
end
end
end
*/
//====================================================================
//脈沖邊沿檢測模塊
//每來一個下降沿就會檢測出來，利用這個
//原理便能測量脈沖的頻率
//===================================================================
reg count_rst;
always @(posedge clk or negedge rst_n)
if (!rst_n) count_rst <= 1'b1;
else count_rst <= led;
reg count_rst_r;
always @ ( posedge clk or negedge rst_n )
if (!rst_n) count_rst_r <= 1'b1;
else count_rst_r <= count_rst;
wire count_an = count_rst_r & (~count_rst);
endmodule

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vhdl測量頻率并用數碼管顯示程序

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