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各位大大:
以下是我的source code ,照理說(shuō)當(dāng)我調(diào)整TA1CCR1 的數(shù)據(jù)時(shí)duty cycle就會(huì)隨之改變,但是不管我數(shù)值改多少duty cycle都沒(méi)有變,會(huì)是我clock選擇的問(wèn)題嗎?
在麻煩各位前輩幫幫我看一下了>< 謝謝.
int main(void)
{
// Stop watchdog
WDTCTL = WDTPW + WDTHOLD;
UCS_init();
P8DIR |= BIT4;
P8SEL |= BIT4;
InitSystemCLK();
TA1CCR1 = 0;
__enable_interrupt();
// LPM0 (shut down the CPU) with interrupts enabled
//__bis_SR_register(CPUOFF | GIE);
while(1)
{
}
}
// This will be called when timer counts to TACCR1.
#pragma vector=TIMER1_A0_VECTOR
__interrupt void TIMER1_A0_ISR(void)
{
int new_ccr1 = 2000;
// Clear interrupt flag
TA1CCTL1 &= ~CCIFG;
TA1CCR1 = new_ccr1 ;
}
void UCS_init(void)
{
// Set Vcore to accomodate for max. allowed system speed
PMM_setVCore(PMM_BASE,PMMCOREV_3); // Used PMM_CORE_LEVEL_3
// Initialize LFXT1
UCSCTL6 &= ~(XT1OFF); // Enable XT1
UCSCTL6 |= XCAP_3; // Internal load cap 12pF
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
} while (UCSCTL7 & XT1LFOFFG); // Test XT1 fault flag
// Use 32.768kHz XTAL as reference
// LFXT_Start(XT1DRIVE_3);
// Setup UCS
UCSCTL3 |= SELREF_0; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_0; // Set ACLK = REFO
// Initialize DCO to 2.45MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_7; // Set RSELx for DCO = 24 MHz
UCSCTL2 = FLLD_0 | 611; // Set DCO Multiplier for 20MHz
// (N + 1) * FLLRef = Fdco
// (611 + 1) * 32768 = 20MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(625000);
// Loop until XT1, XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
__no_operation();
}
void InitSystemCLK(void)
{
// Setup TA1
// PWM period
TA1CCR0 = 4500;
TA1CTL = TASSEL_2 | MC_1 ; // SMCLK, upmode, clear TAR
TA1CCTL0 = OUTMOD_7 | CCIE; // CCR0 interrupt enabled
}
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