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此外部中斷的設(shè)置我完全是采用了寄存器的操作，沒(méi)有用一個(gè)庫(kù)函數(shù)來(lái)實(shí)現(xiàn)的，這樣做設(shè)置是很慢的，一位一位的校準(zhǔn)，但是我喜歡這樣做。效果如同我想的一樣！！！！！！！！！！，與天津第四項(xiàng)目部宿舍
- #include "stm32f10x.h"
- GPIO_InitTypeDef GPIO_InitStructure;
- void mysysint();
- void my_EXTI_int();
- int main(void)
- {
- mysysint();//RCC初始化，時(shí)鐘設(shè)置72MHZ
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);//使能APB2時(shí)鐘
- /* Configure PD0 and PD2 in output pushpull mode */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9| GPIO_Pin_10| GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_Init(GPIOD, &GPIO_InitStructure);
- my_EXTI_int();
- while(1);
-
- }
- void my_EXTI_int()//呼呼！
- {
- /* PA8被我設(shè)置成輸入,上啦、下拉 */
- GPIOA->CRH=0x44444448;
- /*配置PA的8-11腳為中斷輸入線*/
- AFIO->EXTICR[2]=0x0;
- /*設(shè)置外部中斷線8中斷請(qǐng)求開(kāi)啟其他的都關(guān)閉*/
- EXTI->IMR=0x00000100;
- /*下降沿觸發(fā)*/
- EXTI->FTSR=0x00000100;
- /*EXTI9_5的優(yōu)先級(jí)設(shè)為10*/
- NVIC->IP[23]=10;
- /*開(kāi)啟23號(hào)中斷即EXTI9_5，關(guān)閉其他所有外部的中斷*/
- NVIC->ISER[0]=0x00800000;
-
-
- }
- void mysysint()//系統(tǒng)初始化程序
- {
- ErrorStatus HSEStartUpStatus;//說(shuō)明標(biāo)志位
- RCC_DeInit();//所有外設(shè)全部缺省設(shè)置
- /* Enable HSE */
- RCC_HSEConfig(RCC_HSE_ON);
- /* Wait till HSE is ready and if Time out is reached exit */
- HSEStartUpStatus = RCC_WaitForHSEStartUp();
- if(HSEStartUpStatus == SUCCESS)//啟動(dòng)成功
- {
- /*這兩條FLASH指令必須加上，不知為啥？不加上就運(yùn)行幾秒后出錯(cuò)，參照系統(tǒng)初始化*/
- /* Enable The Prefetch Buffer */
- FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);//FLASH緩存開(kāi)啟
- /* Configure the Latency cycle: Set 2 Latency cycles */
- FLASH_SetLatency(FLASH_Latency_2); //設(shè)置FLASH這些位表示SYSCLK(系統(tǒng)時(shí)鐘)周期與閃存訪問(wèn)時(shí)間的比例,為010：兩個(gè)等待狀態(tài)，當(dāng) 48MHz < SYSCLK ≤ 72MHz
- /* Set PLL clock output to 72MHz using HSE (8MHz) as entry clock */
- RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);//外部時(shí)鐘為8M，PLL的輸入時(shí)鐘=8MHZ，倍頻系數(shù)9，
- /* Configure HCLK such as HCLK = SYSCLK */
- RCC_HCLKConfig(RCC_SYSCLK_Div1);//設(shè)置了啦AHB分頻器的分頻系數(shù)=1，即HCLK=SYSCLK=72MHZ
- /* Configure PCLK1 such as PCLK1 = HCLK/2 */
- RCC_PCLK1Config(RCC_HCLK_Div2);//設(shè)置了APB1外設(shè)的時(shí)鐘頻率最大是36M這里是APB1的分頻器設(shè)為2,PCLK1=HCLK/2=72/2=36MHZ正好是最大值
- /* Configure PCLK2 such as PCLK2 = HCLK */
- RCC_PCLK2Config(RCC_HCLK_Div1);//設(shè)置PLCK2=HCLK=72MHZ，的APB2分頻器=1
- /* Select the PLL as system clock source */
- RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//設(shè)置了SYSCLK的提供者為PLL，頻率由上面算出=72MHZ
- /* disable PLL Ready interrupt */
- RCC_ITConfig(RCC_IT_PLLRDY, DISABLE);//PLL中斷關(guān)閉
- /* disable PLL Ready interrupt */
- RCC_ITConfig(RCC_IT_HSERDY,DISABLE);//HSE中斷關(guān)閉
- /* disable PLL Ready interrupt */
- RCC_ITConfig(RCC_IT_HSIRDY, DISABLE); //HSI中斷關(guān)閉
- /* disable PLL Ready interrupt */
- RCC_ITConfig(RCC_IT_LSERDY, DISABLE); //LSE中斷關(guān)閉
- /* disable PLL Ready interrupt */
- RCC_ITConfig(RCC_IT_LSIRDY, DISABLE); //LSI中斷關(guān)閉
- /* PLL clock divided by 1.5 used as USB clock source */
- RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);//設(shè)置USB的時(shí)鐘為=72、1.5=48mhz
- /* Configure ADCCLK such as ADCCLK = PCLK2/2 */
- RCC_ADCCLKConfig(RCC_PCLK2_Div2);//設(shè)置ADC時(shí)鐘=PCLK2/2= 36MHZ
- /* disable the LSE */
- RCC_LSEConfig(RCC_LSE_OFF);//外部低速晶振關(guān)閉
- /*DISable the RTC clock */
- RCC_RTCCLKCmd(DISABLE);
- /* DISable the Clock Security System */
- RCC_ClockSecuritySystemCmd(DISABLE);
- /* Enable the PLL */
- RCC_PLLCmd(ENABLE);//使能PLL
-
-
-
- /* PLL ans system clock config */
- }
- else
- {
- /* Add here some code to deal with this error */
- }
-
-
- }
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