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system_stm32f10x.c時(shí)鐘系統(tǒng)的設(shè)置

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ID:72519 發(fā)表于 2015-1-23 03:50 | 只看該作者 回帖獎(jiǎng)勵(lì) |倒序?yàn)g覽 |閱讀模式
  1. /**
  2.   ******************************************************************************
  3.   * @file    GPIO/IOToggle/system_stm32f10x.c
  4.   * @author  MCD Application Team
  5.   * @version V3.4.0
  6.   * @date    10/15/2010
  7.   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
  8.   ******************************************************************************
  9.   *
  10.   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  11.   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  12.   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  13.   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  14.   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  15.   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  16.   *
  17.   * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
  18.   ******************************************************************************
  19.   */
  20. /** @addtogroup CMSIS
  21.   * @{
  22.   */
  23. /** @addtogroup stm32f10x_system
  24.   * @{
  25.   */

  27. /** @addtogroup STM32F10x_System_Private_Includes
  28.   * @{
  29.   */
  30. #include "stm32f10x.h"
  31. /**
  32.   * @}
  33.   */
  34. /** @addtogroup STM32F10x_System_Private_TypesDefinitions
  35.   * @{
  36.   */
  37. /**
  38.   * @}
  39.   */
  40. /** @addtogroup STM32F10x_System_Private_Defines
  41.   * @{
  42.   */
  43. /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
  44.    frequency (after reset the HSI is used as SYSCLK source)
  45.   
  46.    IMPORTANT NOTE:
  47.    ==============
  48.    1. After each device reset the HSI is used as System clock source.
  49.    2. Please make sure that the selected System clock doesn't exceed your device's
  50.       maximum frequency.
  51.      
  52.    3. If none of the define below is enabled, the HSI is used as System clock
  53.     source.
  54.    4. The System clock configuration functions provided within this file assume that:
  55.         - For Low, Medium and High density Value line devices an external 8MHz
  56.           crystal is used to drive the System clock.
  57.         - For Low, Medium and High density devices an external 8MHz crystal is
  58.           used to drive the System clock.
  59.         - For Connectivity line devices an external 25MHz crystal is used to drive
  60.           the System clock.
  61.      If you are using different crystal you have to adapt those functions accordingly.
  62.     */
  63.    
  64. #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)//如果定義了這些系統(tǒng)時(shí)鐘將設(shè)為24M，如果沒(méi)有定義則為72M
  65. /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
  66. #define SYSCLK_FREQ_24MHz  24000000
  67. #else
  68. /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
  69. /* #define SYSCLK_FREQ_24MHz  24000000 */
  70. /* #define SYSCLK_FREQ_36MHz  36000000 */
  71. /* #define SYSCLK_FREQ_48MHz  48000000 */
  72. /* #define SYSCLK_FREQ_56MHz  56000000 */
  73. #define SYSCLK_FREQ_72MHz  72000000      //系統(tǒng)時(shí)鐘默認(rèn)值的定義 ，如果沒(méi)有定義外部高速時(shí)鐘則用內(nèi)部高速時(shí)鐘，為8000000
  74. #endif
  75. /*!< Uncomment the following line if you need to use external SRAM mounted
  76.      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
  77.      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
  78. #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)//內(nèi)外部SRAM選擇
  79. /* #define DATA_IN_ExtSRAM */
  80. #endif
  81. /*!< Uncomment the following line if you need to relocate your vector Table in
  82.      Internal SRAM. */
  83. /* #define VECT_TAB_SRAM */
  84. #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. //向量表的基址偏移量
  85.                                   This value must be a multiple of 0x100. */

  87. /**
  88.   * @}
  89.   */
  90. /** @addtogroup STM32F10x_System_Private_Macros
  91.   * @{
  92.   */
  93. /**
  94.   * @}
  95.   */
  96. /** @addtogroup STM32F10x_System_Private_Variables
  97.   * @{
  98.   */
  99. /*******************************************************************************
  100. *  Clock Definitions;以下為把系統(tǒng)時(shí)鐘的定義值傳給系統(tǒng)內(nèi)核時(shí)鐘變量,如果沒(méi)有定義外部高速時(shí)鐘則用內(nèi)部高速時(shí)鐘，為8M
  101. *******************************************************************************/
  102. #ifdef SYSCLK_FREQ_HSE
  103.   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
  104. #elif defined SYSCLK_FREQ_24MHz
  105.   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
  106. #elif defined SYSCLK_FREQ_36MHz
  107.   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
  108. #elif defined SYSCLK_FREQ_48MHz
  109.   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
  110. #elif defined SYSCLK_FREQ_56MHz
  111.   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
  112. #elif defined SYSCLK_FREQ_72MHz
  113.   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
  114. #else /*!< HSI Selected as System Clock source */
  115.   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) 如果沒(méi)有定義外部高速時(shí)鐘則用內(nèi)部高速時(shí)鐘，為8000000*/
  116. #endif
  117. __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};//AHB配方表
  118. /**
  119.   * @}
  120.   */
  121. /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
  122.   * @{
  123.   */
  124. /*********************************************************************************
  125.                以下為函數(shù)聲明
  126. *********************************************************************************/
  127. static void SetSysClock(void); //設(shè)置系統(tǒng)時(shí)鐘的函數(shù)聲明
  128. //以下為根據(jù)不同的系統(tǒng)時(shí)鐘的定義來(lái)聲明用到的相應(yīng)的函數(shù)，為后面的函數(shù)調(diào)用做好準(zhǔn)備
  129. #ifdef SYSCLK_FREQ_HSE
  130.   static void SetSysClockToHSE(void);
  131. #elif defined SYSCLK_FREQ_24MHz
  132.   static void SetSysClockTo24(void);
  133. #elif defined SYSCLK_FREQ_36MHz
  134.   static void SetSysClockTo36(void);
  135. #elif defined SYSCLK_FREQ_48MHz
  136.   static void SetSysClockTo48(void);
  137. #elif defined SYSCLK_FREQ_56MHz
  138.   static void SetSysClockTo56(void);
  139. #elif defined SYSCLK_FREQ_72MHz
  140.   static void SetSysClockTo72(void);
  141. #endif
  142. #ifdef DATA_IN_ExtSRAM //外部SRAM選擇后的初始化函數(shù)聲明
  143.   static void SystemInit_ExtMemCtl(void);
  144. #endif /* DATA_IN_ExtSRAM */
  145. /**
  146.   * @}
  147.   */
  148. /** @addtogroup STM32F10x_System_Private_Functions
  149.   * @{
  150.   */
  151. /**
  152.   * @brief  Setup the microcontroller system
  153.   *         Initialize the Embedded Flash Interface, the PLL and update the
  154.   *         SystemCoreClock variable.
  155.   * @note   This function should be used only after reset.
  156.   * @param  None
  157.   * @retval None
  158.   */
  159. void SystemInit (void)//系統(tǒng)初始化函數(shù)，設(shè)置系統(tǒng)的時(shí)鐘及時(shí)鐘中斷（在startup_stm32f10x_md.s中調(diào)用）(復(fù)位RCC時(shí)鐘配置為默認(rèn)狀態(tài)，直到設(shè)置時(shí)鐘函數(shù))
  160. {
  161.   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  162.   /* Set HSION bit */
  163.   RCC->CR |= (uint32_t)0x00000001; //內(nèi)部高速時(shí)鐘使能,內(nèi)部8MHz時(shí)鐘開(kāi)啟
  164.   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
  165. #ifndef STM32F10X_CL
  166.   RCC->CFGR &= (uint32_t)0xF8FF0000;//MCO微控制器沒(méi)有時(shí)鐘輸出(對(duì)外部引腳),ADC預(yù)分頻PCLK2 2分頻后作為ADC時(shí)鐘,APB預(yù)分頻HCLK不分頻,AHB預(yù)分頻SYSCLK不分頻,HSI作為系統(tǒng)時(shí)鐘
  167.                                     //HSI作為系統(tǒng)時(shí)鐘輸出（已輸出），SYSCLK=PCLK=PCLK1=PCLK2=8M，ADCCLK=1/2(PCLK2)=4M
  168. #else
  169.   RCC->CFGR &= (uint32_t)0xF0FF0000;//同上；RCC->CFGR的27位為保留位始終為0 ，HSI作為系統(tǒng)時(shí)鐘輸出（未輸出原因?yàn)槲淳幾g）
  170. #endif /* STM32F10X_CL */  

  172.   /* Reset HSEON, CSSON and PLLON bits */
  173.   RCC->CR &= (uint32_t)0xFEF6FFFF;//時(shí)鐘監(jiān)測(cè)器關(guān)閉,HSE振蕩器關(guān)閉
  174.   /* Reset HSEBYP bit */
  175.   RCC->CR &= (uint32_t)0xFFFBFFFF;//外部4-25MHz振蕩器沒(méi)有旁路
  176.   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  177.   RCC->CFGR &= (uint32_t)0xFF80FFFF; //PLL時(shí)鐘1.5倍分頻作為USB時(shí)鐘,PLL 2倍頻輸出,HSE不分頻,HSI時(shí)鐘2分頻后作為PLL輸入時(shí)鐘
  178.                                      //PLLCLK=HSICLK=8M（還未輸出）,HSECLK=HSEOSC,USBCLK=PLLCLK/1.5 ，除PLL外其他分頻系數(shù)都為0
  179. #ifdef STM32F10X_CL
  180.   /* Reset PLL2ON and PLL3ON bits */
  181.   RCC->CR &= (uint32_t)0xEBFFFFFF;//CR中的26和28位置0
  182.   /* Disable all interrupts and clear pending bits  */
  183.   RCC->CIR = 0x00FF0000;//清除中斷標(biāo)志，關(guān)閉一些中斷
  184.   /* Reset CFGR2 register */
  185.   RCC->CFGR2 = 0x00000000; //沒(méi)有此寄存器
  186. #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  187.   /* Disable all interrupts and clear pending bits  */
  188.   RCC->CIR = 0x009F0000;//清除中斷標(biāo)志，關(guān)閉一些中斷
  189.   /* Reset CFGR2 register */
  190.   RCC->CFGR2 = 0x00000000; //沒(méi)有此寄存器   
  191. #else
  192.   /* Disable all interrupts and clear pending bits  */
  193.   RCC->CIR = 0x009F0000; //清除中斷標(biāo)志，關(guān)閉一些中斷
  194. #endif /* STM32F10X_CL */
  195.    
  196. #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
  197.   #ifdef DATA_IN_ExtSRAM
  198.     SystemInit_ExtMemCtl();//如果宏定義了外部SRAM則對(duì)其初始化控制
  199.   #endif /* DATA_IN_ExtSRAM */
  200. #endif
  201.   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
  202.   /* Configure the Flash Latency cycles and enable prefetch buffer */
  203.   SetSysClock();//設(shè)置系統(tǒng)時(shí)鐘
  204. #ifdef VECT_TAB_SRAM
  205.   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. 向量表放在內(nèi)部SRAM中*/
  206. #else
  207.   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. 向量表放在內(nèi)部flash中*/
  208. #endif
  209. }
  210. /**
  211.   * @brief  Update SystemCoreClock according to Clock Register Values
  212.   * @note   None
  213.   * @param  None
  214.   * @retval None
  215.   */
  216. void SystemCoreClockUpdate (void)
  217. {
  218.   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
  219. #ifdef  STM32F10X_CL
  220.   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
  221. #endif /* STM32F10X_CL */
  222. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  223.   uint32_t prediv1factor = 0;
  224. #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
  225.    
  226.   /* Get SYSCLK source -------------------------------------------------------*/
  227.   tmp = RCC->CFGR & RCC_CFGR_SWS;

  229.   switch (tmp)
  230.   {
  231.     case 0x00:  /* HSI used as system clock */
  232.       SystemCoreClock = HSI_VALUE;
  233.       break;
  234.     case 0x04:  /* HSE used as system clock */
  235.       SystemCoreClock = HSE_VALUE;
  236.       break;
  237.     case 0x08:  /* PLL used as system clock */
  238.       /* Get PLL clock source and multiplication factor ----------------------*/
  239.       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
  240.       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
  241.      
  242. #ifndef STM32F10X_CL     
  243.       pllmull = ( pllmull >> 18) + 2;
  244.      
  245.       if (pllsource == 0x00)
  246.       {
  247.         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  248.         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
  249.       }
  250.       else
  251.       {
  252. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  253.        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
  254.        /* HSE oscillator clock selected as PREDIV1 clock entry */
  255.        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
  256. #else
  257.         /* HSE selected as PLL clock entry */
  258.         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
  259.         {/* HSE oscillator clock divided by 2 */
  260.           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
  261.         }
  262.         else
  263.         {
  264.           SystemCoreClock = HSE_VALUE * pllmull;
  265.         }
  266. #endif
  267.       }
  268. #else
  269.       pllmull = pllmull >> 18;
  270.      
  271.       if (pllmull != 0x0D)
  272.       {
  273.          pllmull += 2;
  274.       }
  275.       else
  276.       { /* PLL multiplication factor = PLL input clock * 6.5 */
  277.         pllmull = 13 / 2;
  278.       }
  279.            
  280.       if (pllsource == 0x00)
  281.       {
  282.         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  283.         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
  284.       }
  285.       else
  286.       {/* PREDIV1 selected as PLL clock entry */
  287.       
  288.         /* Get PREDIV1 clock source and division factor */
  289.         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
  290.         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
  291.       
  292.         if (prediv1source == 0)
  293.         {
  294.           /* HSE oscillator clock selected as PREDIV1 clock entry */
  295.           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;         
  296.         }
  297.         else
  298.         {/* PLL2 clock selected as PREDIV1 clock entry */
  299.          
  300.           /* Get PREDIV2 division factor and PLL2 multiplication factor */
  301.           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
  302.           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
  303.           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                        
  304.         }
  305.       }
  306. #endif /* STM32F10X_CL */
  307.       break;
  308.     default:
  309.       SystemCoreClock = HSI_VALUE;
  310.       break;
  311.   }

  313.   /* Compute HCLK clock frequency ----------------*/
  314.   /* Get HCLK prescaler */
  315.   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  316.   /* HCLK clock frequency */
  317.   SystemCoreClock >>= tmp;
  318. }
  319. /**
  320.   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
  321.   * @param  None
  322.   * @retval None
  323.   */
  324. static void SetSysClock(void)//根據(jù)不同的宏定義，設(shè)置不同的系統(tǒng)時(shí)鐘
  325. {
  326. #ifdef SYSCLK_FREQ_HSE
  327.   SetSysClockToHSE();
  328. #elif defined SYSCLK_FREQ_24MHz
  329.   SetSysClockTo24();
  330. #elif defined SYSCLK_FREQ_36MHz
  331.   SetSysClockTo36();
  332. #elif defined SYSCLK_FREQ_48MHz
  333.   SetSysClockTo48();
  334. #elif defined SYSCLK_FREQ_56MHz
  335.   SetSysClockTo56();
  336. #elif defined SYSCLK_FREQ_72MHz
  337.   SetSysClockTo72();
  338. #endif

  340. /* If none of the define above is enabled, the HSI is used as System clock
  341.     source (default after reset) */
  342. }
  343. /**
  344.   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
  345.   *          before jump to __main
  346.   * @param  None
  347.   * @retval None
  348.   */
  349. #ifdef DATA_IN_ExtSRAM
  350. /**
  351.   * @brief  Setup the external memory controller.
  352.   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
  353.   *        This function configures the external SRAM mounted on STM3210E-EVAL
  354.   *         board (STM32 High density devices). This SRAM will be used as program
  355.   *         data memory (including heap and stack).
  356.   * @param  None
  357.   * @retval None
  358.   */
  359. void SystemInit_ExtMemCtl(void)
  360. {
  361. /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
  362.   required, then adjust the Register Addresses */
  363.   /* Enable FSMC clock */
  364.   RCC->AHBENR = 0x00000114;

  366.   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  367.   RCC->APB2ENR = 0x000001E0;

  369. /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
  370. /*----------------  SRAM Address lines configuration -------------------------*/
  371. /*----------------  NOE and NWE configuration --------------------------------*/
  372. /*----------------  NE3 configuration ----------------------------------------*/
  373. /*----------------  NBL0, NBL1 configuration ---------------------------------*/

  375.   GPIOD->CRL = 0x44BB44BB;
  376.   GPIOD->CRH = 0xBBBBBBBB;
  377.   GPIOE->CRL = 0xB44444BB;
  378.   GPIOE->CRH = 0xBBBBBBBB;
  379.   GPIOF->CRL = 0x44BBBBBB;
  380.   GPIOF->CRH = 0xBBBB4444;
  381.   GPIOG->CRL = 0x44BBBBBB;
  382.   GPIOG->CRH = 0x44444B44;
  383.   
  384. /*----------------  FSMC Configuration ---------------------------------------*/
  385. /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/

  387.   FSMC_Bank1->BTCR[4] = 0x00001011;
  388.   FSMC_Bank1->BTCR[5] = 0x00000200;
  389. }
  390. #endif /* DATA_IN_ExtSRAM */
  391. #ifdef SYSCLK_FREQ_HSE
  392. /**
  393.   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
  394.   *          and PCLK1 prescalers.
  395.   * @note   This function should be used only after reset.
  396.   * @param  None
  397.   * @retval None
  398.   */
  399. static void SetSysClockToHSE(void)
  400. {
  401.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  403.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
  404.   /* Enable HSE */   
  405.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  407.   /* Wait till HSE is ready and if Time out is reached exit */
  408.   do
  409.   {
  410.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  411.     StartUpCounter++;
  412.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  413.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  414.   {
  415.     HSEStatus = (uint32_t)0x01;
  416.   }
  417.   else
  418.   {
  419.     HSEStatus = (uint32_t)0x00;
  420.   }
  421.   if (HSEStatus == (uint32_t)0x01)
  422.   {
  423. #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
  424.     /* Enable Prefetch Buffer */
  425.     FLASH->ACR |= FLASH_ACR_PRFTBE;
  426.     /* Flash 0 wait state */
  427.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  428. #ifndef STM32F10X_CL
  429.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
  430. #else
  431.     if (HSE_VALUE <= 24000000)
  432. {
  433.       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
  434. }
  435. else
  436. {
  437.       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  438. }
  439. #endif /* STM32F10X_CL */
  440. #endif

  442.     /* HCLK = SYSCLK */
  443.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
  444.      
  445.     /* PCLK2 = HCLK */
  446.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
  447.    
  448.     /* PCLK1 = HCLK */
  449.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
  450.    
  451.     /* Select HSE as system clock source */
  452.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  453.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;   
  454.     /* Wait till HSE is used as system clock source */
  455.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
  456.     {
  457.     }
  458.   }
  459.   else
  460.   { /* If HSE fails to start-up, the application will have wrong clock
  461.          configuration. User can add here some code to deal with this error */
  462.   }
  463. }
  464. #elif defined SYSCLK_FREQ_24MHz
  465. /**
  466.   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
  467.   *          and PCLK1 prescalers.
  468.   * @note   This function should be used only after reset.
  469.   * @param  None
  470.   * @retval None
  471.   */
  472. static void SetSysClockTo24(void)//系統(tǒng)時(shí)鐘設(shè)置為24M：SYSCLK=24M，HCLK=24M，PCLK1=24M（最高36M），PCLK2=24M，ADCCLK=12M,
  473. {
  474.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  476.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
  477.   /* Enable HSE */   
  478.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  480.   /* Wait till HSE is ready and if Time out is reached exit */
  481.   do
  482.   {
  483.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  484.     StartUpCounter++;
  485.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  486.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  487.   {
  488.     HSEStatus = (uint32_t)0x01;
  489.   }
  490.   else
  491.   {
  492.     HSEStatus = (uint32_t)0x00;
  493.   }
  494.   if (HSEStatus == (uint32_t)0x01)
  495.   {
  496. #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
  497.     /* Enable Prefetch Buffer */
  498.     FLASH->ACR |= FLASH_ACR_PRFTBE;
  499.     /* Flash 0 wait state */
  500.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  501.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;   
  502. #endif

  504.     /* HCLK = SYSCLK */
  505.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
  506.      
  507.     /* PCLK2 = HCLK */
  508.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
  509.    
  510.     /* PCLK1 = HCLK */
  511.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
  512.    
  513. #ifdef STM32F10X_CL
  514.     /* Configure PLLs ------------------------------------------------------*/
  515.     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
  516.     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
  517.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
  518.                             RCC_CFGR_PLLMULL6);
  519.     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
  520.     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */      
  521.     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
  522.                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
  523.     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
  524.                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);

  526.     /* Enable PLL2 */
  527.     RCC->CR |= RCC_CR_PLL2ON;
  528.     /* Wait till PLL2 is ready */
  529.     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
  530.     {
  531.     }  
  532. #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
  533.     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
  534.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
  535.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
  536. #else   
  537.     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
  538.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
  539.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
  540. #endif /* STM32F10X_CL */
  541.     /* Enable PLL */
  542.     RCC->CR |= RCC_CR_PLLON;
  543.     /* Wait till PLL is ready */
  544.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
  545.     {
  546.     }
  547.     /* Select PLL as system clock source */
  548.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  549.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
  550.     /* Wait till PLL is used as system clock source */
  551.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
  552.     {
  553.     }
  554.   }
  555.   else
  556.   { /* If HSE fails to start-up, the application will have wrong clock
  557.          configuration. User can add here some code to deal with this error */
  558.   }
  559. }
  560. #elif defined SYSCLK_FREQ_36MHz
  561. /**
  562.   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
  563.   *          and PCLK1 prescalers.
  564.   * @note   This function should be used only after reset.
  565.   * @param  None
  566.   * @retval None
  567.   */
  568. static void SetSysClockTo36(void)//系統(tǒng)時(shí)鐘設(shè)置為36M：SYSCLK=36M，HCLK=36M，PCLK1=36M（最高36M），PCLK2=36M，ADCCLK=18M,
  569. {
  570.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  572.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
  573.   /* Enable HSE */   
  574.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  576.   /* Wait till HSE is ready and if Time out is reached exit */
  577.   do
  578.   {
  579.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  580.     StartUpCounter++;
  581.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  582.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  583.   {
  584.     HSEStatus = (uint32_t)0x01;
  585.   }
  586.   else
  587.   {
  588.     HSEStatus = (uint32_t)0x00;
  589.   }
  590.   if (HSEStatus == (uint32_t)0x01)
  591.   {
  592.     /* Enable Prefetch Buffer */
  593.     FLASH->ACR |= FLASH_ACR_PRFTBE;
  594.     /* Flash 1 wait state */
  595.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  596.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;   

  598.     /* HCLK = SYSCLK */
  599.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
  600.      
  601.     /* PCLK2 = HCLK */
  602.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
  603.    
  604.     /* PCLK1 = HCLK */
  605.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
  606.    
  607. #ifdef STM32F10X_CL
  608.     /* Configure PLLs ------------------------------------------------------*/
  609.    
  610.     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
  611.     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
  612.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
  613.                             RCC_CFGR_PLLMULL9);
  614. /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
  615.     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
  616.       
  617.     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
  618.                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
  619.     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
  620.                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);

  622.     /* Enable PLL2 */
  623.     RCC->CR |= RCC_CR_PLL2ON;
  624.     /* Wait till PLL2 is ready */
  625.     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
  626.     {
  627.     }
  628.    
  629. #else   
  630.     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
  631.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
  632.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
  633. #endif /* STM32F10X_CL */
  634.     /* Enable PLL */
  635.     RCC->CR |= RCC_CR_PLLON;
  636.     /* Wait till PLL is ready */
  637.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
  638.     {
  639.     }
  640.     /* Select PLL as system clock source */
  641.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  642.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
  643.     /* Wait till PLL is used as system clock source */
  644.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
  645.     {
  646.     }
  647.   }
  648.   else
  649.   { /* If HSE fails to start-up, the application will have wrong clock
  650.          configuration. User can add here some code to deal with this error */
  651.   }
  652. }
  653. #elif defined SYSCLK_FREQ_48MHz
  654. /**
  655.   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
  656.   *          and PCLK1 prescalers.
  657.   * @note   This function should be used only after reset.
  658.   * @param  None
  659.   * @retval None
  660.   */
  661. static void SetSysClockTo48(void)//系統(tǒng)時(shí)鐘設(shè)置為48M：SYSCLK=48M，HCLK=48M，PCLK1=24M（最高36M），PCLK2=48M，ADCCLK=24M,
  662. {
  663.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  665.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
  666.   /* Enable HSE */   
  667.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  669.   /* Wait till HSE is ready and if Time out is reached exit */
  670.   do
  671.   {
  672.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  673.     StartUpCounter++;
  674.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  675.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  676.   {
  677.     HSEStatus = (uint32_t)0x01;
  678.   }
  679.   else
  680.   {
  681.     HSEStatus = (uint32_t)0x00;
  682.   }
  683.   if (HSEStatus == (uint32_t)0x01)
  684.   {
  685.     /* Enable Prefetch Buffer */
  686.     FLASH->ACR |= FLASH_ACR_PRFTBE;
  687.     /* Flash 1 wait state */
  688.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  689.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;   

  691.     /* HCLK = SYSCLK */
  692.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
  693.      
  694.     /* PCLK2 = HCLK */
  695.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
  696.    
  697.     /* PCLK1 = HCLK/2 */
  698.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
  699.    
  700. #ifdef STM32F10X_CL
  701.     /* Configure PLLs ------------------------------------------------------*/
  702.     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
  703.     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
  704.       
  705.     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
  706.                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
  707.     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
  708.                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

  710.     /* Enable PLL2 */
  711.     RCC->CR |= RCC_CR_PLL2ON;
  712.     /* Wait till PLL2 is ready */
  713.     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
  714.     {
  715.     }
  716.    
  717.   
  718.     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
  719.     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
  720.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
  721.                             RCC_CFGR_PLLMULL6);
  722. #else   
  723.     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
  724.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
  725.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
  726. #endif /* STM32F10X_CL */
  727.     /* Enable PLL */
  728.     RCC->CR |= RCC_CR_PLLON;
  729.     /* Wait till PLL is ready */
  730.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
  731.     {
  732.     }
  733.     /* Select PLL as system clock source */
  734.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  735.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
  736.     /* Wait till PLL is used as system clock source */
  737.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
  738.     {
  739.     }
  740.   }
  741.   else
  742.   { /* If HSE fails to start-up, the application will have wrong clock
  743.          configuration. User can add here some code to deal with this error */
  744.   }
  745. }
  746. #elif defined SYSCLK_FREQ_56MHz
  747. /**
  748.   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
  749.   *          and PCLK1 prescalers.
  750.   * @note   This function should be used only after reset.
  751.   * @param  None
  752.   * @retval None
  753.   */
  754. static void SetSysClockTo56(void)//系統(tǒng)時(shí)鐘設(shè)置為56M：SYSCLK=56M，HCLK=56M，PCLK1=28M（最高36M），PCLK2=56M，ADCCLK=28M,
  755. {
  756.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  758.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/  
  759.   /* Enable HSE */   
  760.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  762.   /* Wait till HSE is ready and if Time out is reached exit */
  763.   do
  764.   {
  765.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  766.     StartUpCounter++;
  767.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  768.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  769.   {
  770.     HSEStatus = (uint32_t)0x01;
  771.   }
  772.   else
  773.   {
  774.     HSEStatus = (uint32_t)0x00;
  775.   }
  776.   if (HSEStatus == (uint32_t)0x01)
  777.   {
  778.     /* Enable Prefetch Buffer */
  779.     FLASH->ACR |= FLASH_ACR_PRFTBE;
  780.     /* Flash 2 wait state */
  781.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  782.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;   

  784.     /* HCLK = SYSCLK */
  785.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
  786.      
  787.     /* PCLK2 = HCLK */
  788.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
  789.    
  790.     /* PCLK1 = HCLK/2 */
  791.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
  792. #ifdef STM32F10X_CL
  793.     /* Configure PLLs ------------------------------------------------------*/
  794.     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
  795.     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
  796.       
  797.     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
  798.                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
  799.     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
  800.                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

  802.     /* Enable PLL2 */
  803.     RCC->CR |= RCC_CR_PLL2ON;
  804.     /* Wait till PLL2 is ready */
  805.     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
  806.     {
  807.     }
  808.    
  809.   
  810.     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
  811.     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
  812.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
  813.                             RCC_CFGR_PLLMULL7);
  814. #else   
  815.     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
  816.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
  817.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
  818. #endif /* STM32F10X_CL */
  819.     /* Enable PLL */
  820.     RCC->CR |= RCC_CR_PLLON;
  821.     /* Wait till PLL is ready */
  822.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
  823.     {
  824.     }
  825.     /* Select PLL as system clock source */
  826.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  827.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
  828.     /* Wait till PLL is used as system clock source */
  829.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
  830.     {
  831.     }
  832.   }
  833.   else
  834.   { /* If HSE fails to start-up, the application will have wrong clock
  835.          configuration. User can add here some code to deal with this error */
  836.   }
  837. }
  838. #elif defined SYSCLK_FREQ_72MHz
  839. /**
  840.   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
  841.   *          and PCLK1 prescalers.
  842.   * @note   This function should be used only after reset.
  843.   * @param  None
  844.   * @retval None
  845.   */
  846. static void SetSysClockTo72(void)//系統(tǒng)時(shí)鐘設(shè)置為72M：SYSCLK=72M，HCLK=72M，PCLK1=36M（最高36M），PCLK2=72M，ADCCLK=36M,
  847. {
  848.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;//啟動(dòng)計(jì)數(shù)，HSE狀態(tài)

  850.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
  851.   /* Enable HSE */   
  852.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);//HSE使能

  854.   /* Wait till HSE is ready and if Time out is reached exit */
  855.   do //循環(huán)，直到HSE使能成功或者超時(shí)
  856.   {
  857.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  858.     StartUpCounter++;
  859.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  860.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  861.   {
  862.     HSEStatus = (uint32_t)0x01;//HSE使能成功
  863.   }
  864.   else
  865.   {
  866.     HSEStatus = (uint32_t)0x00;//HSE使能不成功
  867.   }
  868.   if (HSEStatus == (uint32_t)0x01)//HSE使能成功
  869.   {
  870.     /* Enable Prefetch Buffer */
  871.     FLASH->ACR |= FLASH_ACR_PRFTBE;//flash緩存使能
  872.     /* Flash 2 wait state */
  873.     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);//
  874.     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;//   

  876.     /* HCLK = SYSCLK */
  877.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;//RCC_CFGR_HPRE_DIV1=0，CFGR中的值不變
  878.      
  879.     /* PCLK2 = HCLK */
  880.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;//RCC_CFGR_PPRE2_DIV1=0，CFGR中的值不變
  881.    
  882.     /* PCLK1 = HCLK/2 */
  883.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//低速APB預(yù)分頻把HCLK 2分頻,APB1CLK=HCLK/2
  884. #ifdef STM32F10X_CL
  885.     /* Configure PLLs ------------------------------------------------------*/
  886.     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
  887.     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
  888.       
  889.     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
  890.                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
  891.     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
  892.                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

  894.     /* Enable PLL2 */
  895.     RCC->CR |= RCC_CR_PLL2ON;
  896.     /* Wait till PLL2 is ready */
  897.     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
  898.     {
  899.     }
  900.    
  901.   
  902.     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
  903.     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
  904.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
  905.                             RCC_CFGR_PLLMULL9);
  906. #else   
  907.     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
  908.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |  //PLL輸入時(shí)鐘源HSI時(shí)鐘2分頻后作為PLL輸入時(shí)鐘,HSE分頻器作為PLL輸入HSE不分頻
  909.                                         RCC_CFGR_PLLMULL)); //PLL倍頻系數(shù)PLL 2倍頻輸出（為了清零其他位）
  910.     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);//PLL輸入時(shí)鐘源HSE時(shí)鐘作為PLL輸入時(shí)鐘,PLL倍頻系數(shù)PLL 9倍頻輸出
  911. #endif /* STM32F10X_CL */
  912.     /* Enable PLL */
  913.     RCC->CR |= RCC_CR_PLLON; //PLL使能
  914.     /* Wait till PLL is ready */
  915.     while((RCC->CR & RCC_CR_PLLRDY) == 0)//等待PLL使能成功
  916.     {
  917.     }
  918.    
  919.     /* Select PLL as system clock source */
  920.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//HSI作為系統(tǒng)時(shí)鐘(為了清零其他位)
  921.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; //PLL輸出作為系統(tǒng)時(shí)鐘  
  922.     /* Wait till PLL is used as system clock source */
  923.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)//等待直到PLL成功用作系統(tǒng)時(shí)鐘源
  924.     {
  925.     }
  926.   }
  927.   else
  928.   { /* If HSE fails to start-up, the application will have wrong clock
  929.          configuration. User can add here some code to deal with this error */
  930.   }
  931. }
  932. #endif
  933. /**
  934.   * @}
  935.   */
  936. /**
  937.   * @}
  938.   */

  940. /**
  941.   * @}
  942.   */   
  943. /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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