算數(shù)運(yùn)算時(shí)FPGA編程設(shè)計(jì)中常會(huì)用到的功能，其規(guī)則直接影響變成效果，調(diào)用use ieee.std_logic_unsigned.all;此程序包對(duì)不同的數(shù)據(jù)類型可以進(jìn)行適當(dāng)?shù)乃銛?shù)運(yùn)算： 1.對(duì)std_logic_vector()可進(jìn)行相同位數(shù)的加減運(yùn)算（被加數(shù)必須和輸出位數(shù)相同）； 2.對(duì)std_logic_vector()可進(jìn)行相乘法運(yùn)算（積的位數(shù)等于倆乘數(shù)位數(shù)之和）；
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity adder_n is
port(a,b:in std_logic_vector(4 downto 0);
c:in std_logic_vector(2 downto 0);
Sum1,sum2:out std_logic_vector(9 downto 0);
sum4,sum3 :out std_logic_vector(4 downto 0) );
end;
Architecture add of adder_n is
begin
Sum1<="00000"&a + b;
Sum2<=a * b;
sum3<=a - b;
sum4<=a + b;
end;
3.對(duì)Integer（整數(shù)）可以進(jìn)行加、減、乘、除和取余運(yùn)算； Library ieee; Useieee.std_logic_1164.all; Useieee.std_logic_unsigned.all; entity adder_n is generic(n:integer:=4);----改變w的值可以改變運(yùn)算寬度 port(a:in integerrange 0 to 4095; dd,b:in integer range 0 to 255; cin:in integer range 0 to 64; Sum1,sum2:out integer range 0 to 4095; ddd:out integer range 0 to 1023; co1,co2:out integer range 0 to 1023); end; Architecture add of adder_n is begin Sum1<=a * b;---a,b一個(gè)可以是常數(shù)，如 Sum1<=2 * b sum2<=a + b; ddd<=a / b;---- 雖然是除，但實(shí)際為商 取整運(yùn)算 co1<=a - dd; co2<= a REM cin; --- 取余 end; | 
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