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 lcd1602液晶的詳細(xì)資料請(qǐng)看：http://www.zg4o1577.cn/mcu/827.html
library ieee;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lcd1602 is
port(clk, reset: in std_logic;
LCD_Data: out std_logic_vector(8 downto 0);
en: out std_logic;
rw: out std_logic);
end lcd1602;
architecture gongneng of lcd1602 is
signal LCD_Clk: std_logic;
signal s : integer range 0 to 10000000;
begin
--50MHz to 5Hz
process(clk, reset)
begin
if reset = '0' then
LCD_Clk <= '0';
s <= 0;
elsif clk'event and clk = '1' then
if s = 10000000 then
s <= 0;
LCD_Clk <= not LCD_Clk;
else
s <= s + 1;
end if;
end if;
end process;
-------------------
rw <='0';
en <= LCD_Clk;
process(LCD_Clk)
variable cnt: std_logic_vector(5 downto 0):="000000";
begin
if Reset='0'then
LCD_Data<="000000001"; -- Reset清屏
--LCD_Data[8..0], 其中LCD_Data[8]對(duì)應(yīng)1602的RS，--LCD_Data[7..0]對(duì)應(yīng)1602的八根數(shù)據(jù)線(xiàn)
cnt:="000000"; --計(jì)數(shù)器清零
elsif rising_edge(LCD_Clk) then
if cnt<"100101" then cnt:=cnt+1;
else cnt:="000000";
end if;
--設(shè)計(jì)計(jì)數(shù)器，每次計(jì)數(shù)間隔LCD_CLK定義的一個(gè)周期
case cnt is
--------------寫(xiě)指令--------------
when "000000"=>LCD_Data<="000111000";--/*設(shè)置8位格式,2行,5*7*/ ,順序2,3的要求
when "000001"=>LCD_Data<="000001100"; --/*整體顯示,關(guān)光標(biāo),光標(biāo)閃爍/ ，順序4的要求
when "000010"=>LCD_Data<="000000001";--清屏，順序5的要求
when "000011"=>LCD_Data<="000000110"; --/*顯示移動(dòng)格式，看最后兩位，10表示光標(biāo)右移，順序6的要求
when "000100"=>LCD_Data<="010000000";--設(shè)定顯示的位置在00H+80H，即顯示屏第一行第一個(gè)位置，順序7的要求
--------------寫(xiě)數(shù)據(jù)---------------
when "000101"=>LCD_Data<="110100000";--空格
when "000110"=>LCD_Data<="110100000";--空格
when "000111"=>LCD_Data<="110100000";--空格
when "001000"=>LCD_Data<="101011001"; --Y
when "001001"=>LCD_Data<="101110101";--u
when "001010"=>LCD_Data<="101101010";--j
when "001011"=>LCD_Data<="101101001";--i
when "001100"=>LCD_Data<="101100001";--a
when "001101"=>LCD_Data<="101101110";--n
when "001110"=>LCD_Data<="101110001";--q
when "001111"=>LCD_Data<="101110101";--u
when "010000"=>LCD_Data<="101100001";--a
when "010001"=>LCD_Data<="101101110";--n
when "010010"=>LCD_Data<="110100000";---空格
when "010011"=>LCD_Data<="110100000";---空格
when "010100"=>LCD_Data<="110100000";---空格
when "010101"=>LCD_Data<="011000000";--設(shè)定顯示的位置在10H+80H，
when "010110"=>LCD_Data<="101000100";---D diangong xueyuan
when "010111"=>LCD_Data<="101101001";---i
when "011000"=>LCD_Data<="101100001";---a
when "011001"=>LCD_Data<="101101110";---n
when "011010"=>LCD_Data<="101100111";---g
when "011011"=>LCD_Data<="101101111";---o
when "011100"=>LCD_Data<="101101110";--n
when "011101"=>LCD_Data<="101100111";---g
when "011110"=>LCD_Data<="110100000";--- 空格
when "011111"=>LCD_Data<="101011000";---X
when "100000"=>LCD_Data<="101110101";---u
when "100001"=>LCD_Data<="101100101";---e
when "100010"=>LCD_Data<="101111001";---y
when "100011"=>LCD_Data<="101110101";---u
when "100100"=>LCD_Data<="101100001";---a
when "100101"=>LCD_Data<="101101110";---n
when others =>LCD_Data<="101000100";
--when "01100"=>LCD_Data<="011000000";--設(shè)定顯示的位置在10H+80H，即顯示屏第2行第一個(gè)位置
end case;
end if;
end process;
end gongneng;
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fuck1 is
Port ( Clk : in std_logic;
Reset:in std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_EN : out std_logic;
LED : out std_logic;
LCD_Data : out std_logic_vector(7 downto 0));
end ;
architecture Behavioral of fuck1 is
type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data);
signal Current_State:state;
type ram2 is array(0 to 7) of std_logic_vector(7 downto 0);
constant cgram:ram2:=(
("00000100"),
("00011011"),
("00001110"),
("00011111"),
("00000100"),
("00011111"),
("00001110"),
("00010101"));
signal Clkk : std_logic;
signal Count : std_logic_vector(20 downto 0);
signal Clk_Out : std_logic;
signal LCD_Clk : std_logic;
begin
LCD_EN <= Clk_Out ;
LED <= Clk_Out;
LCD_RW <= '0' ;
clock :process(Clk,Reset)
begin
if(Reset = '0')then
Count <= (others => '0');
elsif(rising_edge(clk))then
Count <= Count + 1;
if(Count = 0)then
Clk_Out <= not Clk_Out;--fenpin
end if;
end if;
LCD_Clk <= Clk_Out;
end process;
control:process(LCD_Clk,Reset,Current_State)
variable cnt1: std_logic_vector(2 downto 0);
begin
if Reset='0'then
Current_State<=set_dlnf;
cnt1:=(others => '1');
LCD_RS<='0';
elsif rising_edge(LCD_Clk)then
Current_State <= Current_State ;
LCD_RS <= '0';
case Current_State is
when set_dlnf=>
LCD_Data<="00111100";
Current_State<=set_cursor;
when set_cursor=>
LCD_Data<="00000110";
Current_State<=set_dcb;
when set_dcb=>
LCD_Data<="00001111";
Current_State<=set_cgram;
when set_cgram=>
LCD_Data<="01000000";
Current_State<=write_cgram;
when write_cgram=>
LCD_RS<='1';
cnt1:=cnt1+1;
LCD_Data<=cgram(conv_integer(cnt1));
if cnt1 = "111" then
Current_State<=set_ddram;
end if;
when set_ddram=>
LCD_Data<="10000000";
Current_State<=write_LCD_Data;
when write_LCD_Data=>
LCD_RS<='1';
LCD_Data<="00000000";
when others => null;
end case;
end if;
end process;
end ;
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