Library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity ddd is
port(clk:in std_logic;
sec:out std_logic;
Q:out std_logic_vector(17 downto 0));
end ;
Architecture dd of ddd is
type ram2 is array(0 to 59) of std_logic_vector(17 downto 0);
constant cgram:ram2:=(
("100000000000000001"),
("110000000000000011"),
("111000000000000111"),
("111100000000001111"),
("111110000000011111"),
("111111000000111111"),
("111111100001111111"),
("111111110011111111"),
("111111111111111111"),
("111111110011111111"),
("111111100001111111"),
("111111000000111111"),
("111110000000011111"),
("111100000000001111"),
("110000000000000011"),
("100000000000000001"),
("100000000000000001"),
("010000000000000010"),
("001000000000000100"),
("000100000000001000"),
("000010000000010000"),
("000001000000100000"),
("000000100001000000"),
("000000010010000000"),
("000000001100000000"),
("100000000000000000"),
("010000000000000000"),
("001000000000000000"),
("000100000000000000"),
("000010000000000000"),
("000001000000000000"),
("000000100000000000"),
("000000010000000000"),
("000000001000000000"),
("000000000100000000"),
("000000000010000000"),
("000000000001000000"),
("000000000000100000"),
("000000000000010000"),
("000000000000001000"),
("000000000000000100"),
("000000000000000010"),
("000000000000000001"),
("000000000000000010"),
("000000000000000100"),
("000000000000001000"),
("000000000000010000"),
("000000000000100000"),
("000000000001000000"),
("000000000010000000"),
("000000000100000000"),
("000000001000000000"),
("000000010000000000"),
("000000100000000000"),
("000001000000000000"),
("000010000000000000"),
("000100000000000000"),
("001000000000000000"),
("010000000000000000"),
("100000000000000000"));
signal cp:std_logic;
signal ww:integer range 0 to 5000000;
signal cnt:integer range 0 to 59;
begin
process(clk)
begin
if clk'event and clk='1' then
ww<=ww+1;
if ww=0 then
cp<=not cp;
end if;
end if;
end process;
process(cp)
begin
if cp'event and cp='1' then
cnt<=cnt+1;
Q<=cgram(cnt);
end if;
end process;
end;
----------------------------------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity ddd is
port(clk:in std_logic;
sec:out std_logic;
Q:out std_logic_vector(17 downto 0));
end ;
Architecture dd of ddd is
type ram2 is array(0 to 55) of std_logic_vector(19 downto 0);
constant cgram:ram2:=(
--用16進制表示數X“2f”,每個數字代表四位二進制，等于“00101111”
(X"20001"),(X"30003"),(X"38007"),(X"3c00f"),(X"3e01f"),
(X"3f03f"),(X"3f87f"),(X"3fcff"),(X"3ffff"),(X"3fcff"),
(X"3f87f"),(X"3f03f"),(X"3e01f"),(X"3c00f"),(X"38007"),
(X"30003"),(X"20001"),(X"00000"),(X"20000"),(X"10000"),
(X"08000"),(X"04000"),(X"02000"),(X"01000"),(X"00800"),
(X"00400"),(X"00200"),(X"00100"),(X"00080"),(X"00040"),
(X"00020"),(X"00010"),(X"00008"),(X"00004"),(X"00002"),
(X"00001"),(X"00000"),(X"00001"),(X"00002"),(X"00004"),
(X"00008"),(X"00010"),(X"00020"),(X"00040"),(X"00080"),
(X"00100"),(X"00200"),(X"00400"),(X"00800"),(X"01000"),
(X"02000"),(X"04000"),(X"08000"),(X"10000"),(X"20000"),
(X"00000")
);
type ram1 is array(0 to 5) of std_logic_vector(5 downto 0);
constant dat:ram1:=(
--用8進制表示數O“235”,每個數字代表三位二進制數，等于“010 011 101“
(o"01"),(o"02"),(O"04"),(o"10"),(o"20"),(o"40")
);
signal cp:std_logic;
signal ww:integer range 0 to 1000000;
signal cnt:integer range 0 to 55;
begin
process(clk)
begin
if clk'event and clk='1' then
ww<=ww+1;
if ww=0 then
cp<=not cp;
end if;
end if;
end process;
process(cp)
begin
if cp'event and cp='1' then
cnt<=cnt+1;
Q<=cgram(cnt)(17 downto 0);
end if;
end process;
end;
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