Verilog步進(jìn)電機(jī)程序

ID:821845 · 發(fā)表于 2021-3-24 10:34

module step1 (clk0,reset,out,der,x);//狀態(tài)機(jī)module
input clk0,reset,der,x;
output[3:0] out;
reg[3:0] out;
reg[2:0] current;
reg[2:0] current1;
parameter s0=3'b000,s1=3'b001,s2=3'b010,
s3=3'b011,s4=3'b100,s5=3'b101,
s6=3'b110,s7=3'b111;
always@(posedge clk0 or negedge reset )
begin
if(!reset)
begin
current<=s0;
end
else
case(current)
s0:
begin
if(!der)
begin
current<=s7;
current1<=s7;
end
else
begin
current<=s1;
current1<=s1;
end
end
s1:
begin
if(!der)
begin
current<=s0;
current1<=s0;
end
else
begin
current<=s2;
current1<=s2;
end
end
s2:
begin
if(!der)
begin
current<=s1;
current1<=s1;
end
else
begin
current<=s3;
current1<=s3;
end
end
s3:
begin
if(!der)
begin
current<=s2;
current1<=s2;
end
else
begin
current<=s4;
current1<=s4;
end
end
s4:
begin
if(!der)
begin
current<=s3;
current1<=s3;
end
else
begin
current<=s5;
current1<=s5;
end
end
s5:
begin
if(!der)
begin
current<=s4;
current1<=s4;
end
else
begin
current<=s6;
current1<=s6;
end
end
s6:
begin
if(!der)
begin
current<=s5;
current1<=s5;
end
else
begin
current<=s7;
current1<=s7;
end
end
s7:
begin
if(!der)
begin
current<=s6;
current1<=s6;
end
else
begin
current<=s0;
current1<=s0;
end
end
endcase
end
always@(current1 )//or clk0
begin
case(current1)
s0:
begin
out<=4'b1001;
end
s1:
begin
out<=4'b0001;
end
s2:
begin
out<=4'b0011;
end
s3:
begin
out<=4'b0010;
end
s4:
begin
out<=4'b0110;
end
s5:
begin
out<=4'b0100;
end
s6:
begin
out<=4'b1100;
end
s7:
begin
out<=4'b1000;
end
endcase
end
endmodule
module step2 (clk1,a,adj);//分頻module
input clk1;
input[5:0] adj;
output a;
reg a;
reg[25:0] cnt;
reg[15:0] counter;
wire[5:0] adj;
reg[2:0] temp;
always @(posedge clk1)
begin
temp=adj[5]+adj[4]+adj[3]+adj[2]+adj[1]+adj[0];
if(temp==3'd6)
begin
if(cnt <= 32000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd5)
begin
if(cnt <= 16000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd4)
begin
if(cnt <= 12000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd3)
begin
if(cnt <= 10000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd2)
begin
if(cnt <= 8000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd1)
begin
if(cnt <= 6000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
else if(temp==3'd0)
begin
if(cnt <= 4000) cnt <= cnt+1'b1;//0.5MS 1MS 2MS 4MS 8MS 4000 8000 16000 32000 64000
else
begin
cnt <=26'b0;
a=~a;
end
end
end
endmodule
module step (clk,reset,out,der,d);//總體模塊d[5:0]調(diào)速控制端口用6個(gè)撥碼開關(guān)表示全1速度最慢全0時(shí)速度最快其中1（0）的個(gè)數(shù)能表示電機(jī)速度的快慢
input clk ,reset,der,d;
output [3:0]out;
wire p;
wire[5:0] d;
step2 l1 (clk,p,d);//clk系統(tǒng)時(shí)鐘
step1 l2 (p,reset ,out,der);//reset停止轉(zhuǎn)動(dòng) out[3:0]電機(jī)控制輸出端口 der正反方向控制端
endmodule

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Verilog步進(jìn)電機(jī)程序