pfm雙通道驅動 verilog源碼

ID:884524 · 發表于 2021-2-17 14:36

pfm雙通道驅動源碼，驅動雙通道igbt,4路pwm相差90度

module PFMc ( sclk, f_en1,f_en2,Tf_i,Ts_i,Fout1, Fout2 ,Fout3, Fout4
// ,test1
//,t1,test2
);
input sclk ; //晶振50M 20ns
input f_en1; //波形輸出封鎖信號 0封鎖輸出
input f_en2; //波形輸出封鎖信號 0封鎖輸出
input [18:1] Tf_i; //1000000/f us 最大1000000，最小25
//PWM頻率對應周期 f最小1HZ,最大40K
input [6:1]Ts_i; //PWM周期 us 最大31
output reg Fout1 ; //通道1PWM輸出
output reg Fout2 ;
output reg Fout3 ; //通道2PWM輸出
output reg Fout4 ;
// output wire [28:1] test1;
// output wire [28:1] test2;
// output wire [12:1] t1;
//
// assign test1 = f_cnt;
// assign test2 = f_cnt3;
// assign t1 = f1;
reg f_cs1 = 1'd0; //通道1波形使能
reg f_cs2 = 1'd0; //通道2波形使能
reg f_en1_buffer = 1'd0; //通道1波形使能緩存
reg f_en2_buffer = 1'd0; //通道2波形使能緩存
reg rest_n=1'b0; //兩個通道同時關閉時，計數復位，高復位
reg [27:1] f_cnt; //計數值
reg [11:1] f_cnt1 = 11'd0 ; //Ts高電平計數個數
reg [25:1] f_cnt2 = 25'd250 ; //Ts 低電平計數個數
reg [27:1] f_cnt3 ; //總計數值
reg f0 = 1'd0;
reg [11:1] f1=11'd0;
reg [26:1] f2=26'd0,f3=26'd0;
reg [25:1] f4=25'd0,f5=25'd0;
reg [27:1] f6=27'd0,f7=27'd0;
reg [11:1] f8=11'd0;
reg [18:1] Tf_buffer=18'd0;
reg [6:1]Ts_buffer=6'd0;
reg [18:1] Tf=18'd10000;
reg [6:1]Ts=6'd0;
always @( Ts or Tf ) begin //參數設置改變后，對參數初始化
f_cnt1 = Ts*50 ; //(Ts*1000)/20; //Ts高電平計數個數
f_cnt2 = Tf*25; //對應1/2 f個周期計數個數
f_cnt3 = Tf*25<<2 ; //4個驅動方波輸出周期
f0 = 1'd0; //4個電平翻轉狀態 PFM1上升沿
f1 = Ts*50; //PFM1 下降沿
f2 = Tf*25<<1 ; //PFM2上升沿
f3= (Tf*25<<1)+Ts*50; //PFM2 下降沿
f4 =Tf*25; //PFM3上升沿
f5 =Tf*25+Ts*50; //PFM3 下降沿
f6 = (Tf*25<<1)+Tf*25; //PFM4上升沿
f7 = (Tf*25<<1)+Tf*25+Ts*50; //PFM4 下降沿
f8 = Ts*50-Tf*25;
end
always @( f_cs1 or f_cs2 ) begin //兩個通道都關閉時，計數復位
rest_n = !(f_cs1 || f_cs2);
end
//pwm 低電平狀態下使能信號生效
always@( posedge sclk or negedge Fout1 or negedge Fout2 or negedge Fout3 or negedge Fout4 ) begin
if( Fout1==1'b0 || Fout2==1'b0 )
f_cs1 <= f_en1_buffer ;
else f_cs1 <= 1'b1;
if( Fout3==1'b0 || Fout4==1'b0 )
f_cs2 <= f_en2_buffer ;
else f_cs2 <= 1'b1;
end
always@( posedge sclk or posedge rest_n ) begin //通道1 2循環
f_en1_buffer <= f_en1;
f_en2_buffer <= f_en2;
if( rest_n==1'b1 ) begin //封閉后計數復位
f_cnt <= 27'd0;
Tf_buffer <= Tf_i; //f,Ts數據緩存2個時鐘周期
Ts_buffer <= Ts_i;
end
else begin
if( f_cnt>=(f_cnt3+1'b1) ) begin //循環計數復位
f_cnt <= 27'd0;
Tf_buffer <= Tf_i;
Ts_buffer <= Ts_i;
end
else begin
f_cnt <= f_cnt+1'b1;
if( f_cnt==27'd10) begin
Tf<=Tf_buffer;
Ts<=Ts_buffer;
end
end
end
end
always@( posedge sclk ) begin //PWM輸出控制
if(f_cs1==1'b0) begin //通道1，
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
else begin
if( f_cs1 ) begin
case ( f_cnt )
f0: Fout1 <= 1'b1;
f1: Fout2 <= 1'b1;
f2: Fout1 <= 1'b0;
f3: Fout2 <= 1'b0;
endcase
end
else begin
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
end
if ( f_cs2 ==1'b0) begin //通道2
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
else begin
if( f_cs2 ) begin
case(f_cnt)
f4: Fout3 <= 1'b1;
f5: Fout4 <= 1'b1;
f6: Fout3 <= 1'b0;
f7: Fout4 <= 1'b0;
endcase
if(f_cnt1>=f_cnt2) begin
if(f_cnt==f8)begin
Fout4 <= 1'b0;
end
end
end
else begin
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
end
end
endmodule
/*
module PFMc ( sclk, f_en1,f_en2,f_i,Ts_i,Fout1, Fout2 ,Fout3, Fout4
// ,test1,t1,test2
);
input sclk ; //晶振50M 20ns
input f_en1; //波形輸出封鎖信號 0封鎖輸出
input f_en2; //波形輸出封鎖信號 0封鎖輸出
input [16:1] f_i; //PWM頻率 Hz 最小1HZ,最大40K
input [6:1]Ts_i; //PWM周期 us 最大31
output reg Fout1 ; //通道1PWM輸出
output reg Fout2 ;
output reg Fout3 ; //通道2PWM輸出
output reg Fout4 ;
// output wire [28:1] test1;
// output wire [28:1] test2;
// output wire [12:1] t1;
//
// assign test1 = f_cnt;
// assign test2 = f_cnt3;
// assign t1 = f1;
reg f_cs1 = 1'd0; //通道1波形使能
reg f_cs2 = 1'd0; //通道2波形使能
reg f_en1_buffer = 1'd0; //通道1波形使能緩存
reg f_en2_buffer = 1'd0; //通道2波形使能緩存
reg rest_n=1'b0; //兩個通道同時關閉時，計數復位，高復位
reg [27:1] f_cnt; //計數值
reg [11:1] f_cnt1 = 11'd0 ; //Ts高電平計數個數
reg [25:1] f_cnt2 = 25'd250 ; //Ts 低電平計數個數
reg [27:1] f_cnt3 ; //總計數值
reg f0 = 1'd0;
reg [11:1] f1=11'd0;
reg [26:1] f2=26'd0,f3=26'd0;
reg [25:1] f4=25'd0,f5=25'd0;
reg [27:1] f6=27'd0,f7=27'd0;
reg [11:1] f8=11'd0;
reg [17:1] f_buffer=17'd0;
reg [6:1]Ts_buffer=6'd0;
reg [17:1] f=17'd40000;
reg [6:1]Ts=6'd0;
always @( Ts or f ) begin //參數設置改變后，對參數初始化
f_cnt1 = Ts*50 ; //(Ts*1000)/20; //Ts高電平計數個數
f_cnt2 = (1000000/f)*25; //對應1/2 f個周期計數個數
f_cnt3 = (1000000/f)*25<<2 ; //4個驅動方波輸出周期
f0 = 1'd0; //4個電平翻轉狀態 PFM1上升沿
f1 = Ts*50; //PFM1 下降沿
f2 = (1000000/f)*25<<1 ; //PFM2上升沿
f3= {(1000000/f)*25<<1}+Ts*50; //PFM2 下降沿
f4 =(1000000/f)*25; //PFM3上升沿
f5 =(1000000/f)*25+Ts*50; //PFM3 下降沿
f6 = {(1000000/f)*25<<1}+(1000000/f)*25; //PFM4上升沿
f7 = {(1000000/f)*25<<1}+{(1000000/f)*25}+Ts*50; //PFM4 下降沿
f8 = Ts*50-(1000000/f)*25;
end
always @( f_cs1 or f_cs2 ) begin //兩個通道都關閉時，計數復位
rest_n = !(f_cs1 || f_cs2);
end
always@( posedge sclk or negedge Fout1 or negedge Fout2 or negedge Fout3 or negedge Fout4 ) begin
if( Fout1==1'b0 || Fout2==1'b0 )
f_cs1 <= f_en1_buffer ;
else f_cs1 <= 1'b1;
if( Fout3==1'b0 || Fout4==1'b0 )
f_cs2 <= f_en2_buffer ;
else f_cs2 <= 1'b1;
end
always@( posedge sclk or posedge rest_n ) begin //通道1 2循環
f_en1_buffer <= f_en1;
f_en2_buffer <= f_en2;
if( rest_n==1'b1 ) begin //封閉后計數復位
f_cnt <= 27'd0;
f_buffer <= f_i; //f,Ts數據緩存2個時鐘周期
Ts_buffer <= Ts_i;
end
else begin
if( f_cnt>=(f_cnt3+1'b1) ) begin //循環計數復位
f_cnt <= 27'd0;
f_buffer <= f_i;
Ts_buffer <= Ts_i;
end
else begin
f_cnt <= f_cnt+1'b1;
if( f_cnt==27'd10) begin
f<=f_buffer;
Ts<=Ts_buffer;
end
end
end
end
always@( posedge sclk ) begin //PWM輸出控制
if(f_cs1==1'b0) begin //通道1，
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
else begin
if( f_cs1 ) begin
case ( f_cnt )
f0: Fout1 <= 1'b1;
f1: Fout2 <= 1'b1;
f2: Fout1 <= 1'b0;
f3: Fout2 <= 1'b0;
endcase
end
else begin
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
end
if ( f_cs2 ==1'b0) begin //通道2
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
else begin
if( f_cs2 ) begin
case(f_cnt)
f4: Fout3 <= 1'b1;
f5: Fout4 <= 1'b1;
f6: Fout3 <= 1'b0;
f7: Fout4 <= 1'b0;
endcase
if(f_cnt1>=f_cnt2) begin
if(f_cnt==f8)begin
Fout4 <= 1'b0;
end
end
end
else begin
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
end
end
endmodule
*/
/*
//IGBT 波形發生 2個通道
module PFMc ( sclk, f_en1,f_en2,f_i,Ts_i,Fout1, Fout2 ,Fout3, Fout4,test);
input sclk ; //晶振50M 20ns
input f_en1; //波形輸出封鎖信號 0封鎖輸出
input f_en2; //波形輸出封鎖信號 0封鎖輸出
input [17:1] f_i; //PWM頻率 Hz 最小1HZ,最大40K
input [6:1]Ts_i; //PWM周期 us 最大25
output reg Fout1 ; //通道1PWM輸出
output reg Fout2 ;
output reg Fout3 ; //通道2PWM輸出
output reg Fout4 ;
output reg test ;
reg f_cs1 = 1'd0; //通道1波形使能
reg f_cs2 = 1'd0; //通道2波形使能
reg [28:1] f_cnt = 28'd0 ;
reg [12:1] f_cnt1 = 12'd0 ; //Ts高電平計數個數
reg [26:1] f_cnt2 = 26'd250 ; //Ts 低電平計數個數
reg [28:1] f_cnt3 ;
reg f0 = 1'd0;
reg [12:1] f1=12'd0;
reg [27:1] f2=27'd0,f3=27'd0;
reg [28:1] f4=28'd0,f5=28'd0;
reg [28:1] f6=28'd0,f7=28'd0;
reg [12:1] f8=12'd0;
reg [17:1] f_buffer=17'd0;
reg [6:1]Ts_buffer=6'd0;
reg [17:1] f=17'd40000;
reg [6:1]Ts=6'd0;
always@(posedge sclk or negedge f_en1) begin //測試
if(!f_en1) begin
test <= 1'b1;
end
else if(f_cnt == 28'd1)
test <= ~test;
end
always @( posedge sclk ) begin //TS f參數緩存1個周期，在1個周期完后生效
if( f_cnt == 28'd0 ) begin
f_buffer <= f_i;
Ts_buffer <= Ts_i;
end
if( f_cnt1 < f_cnt2 ) begin
if(f_cnt == f_cnt3) begin
f<=f_buffer;
Ts<=Ts_buffer;
end
end
if( f_cnt1 >= f_cnt2 ) begin
if(f_cnt == f8) begin
f<=f_buffer;
Ts<=Ts_buffer;
end
end
end
always @( Ts or f ) begin //參數設置改變后，對參數初始化
f_cnt1 = Ts*50 ; //(Ts*1000)/20; //Ts高電平計數個數
f_cnt2 = (1000000/f)*25; //對應1/2 f個周期計數個數
f_cnt3 = (1000000/f)*25<<2 ; //4個驅動方波輸出周期
f0 = 1 'd0; //4個電平翻轉狀態 PFM1上升沿
f1 = Ts*50; //PFM1 下降沿
f2 = (1000000/f)*25<<1 ; //PFM2上升沿
f3= {(1000000/f)*25<<1}+Ts*50; //PFM2 下降沿
f4 =(1000000/f)*25; //PFM3上升沿
f5 =(1000000/f)*25+Ts*50; //PFM3 下降沿
f6 = {(1000000/f)*25<<1}+(1000000/f)*25; //PFM4上升沿
f7 = {(1000000/f)*25<<1}+{(1000000/f)*25}+Ts*50; //PFM4 下降沿
f8 = Ts*50-(1000000/f)*25;
end
always@( posedge sclk or posedge f_en1 or posedge f_en2) begin //波形輸出期間，禁止關斷
if(f_en1)
if( Fout1 || Fout2 )
f_cs1 <= 1'd1 ;
else f_cs1 <=f_en1 ;
else f_cs1 <= 1'b0;
if(f_en2)
if( Fout3 || Fout4 )
f_cs2 <= 1'd1 ;
else f_cs2 <=f_en2 ;
else f_cs2 <= 1'b0;
end
always@( posedge sclk or posedge f_cs1 or posedge f_cs2 ) begin //通道1 2循環
if( f_cs1 || f_cs2 ) begin //使能
f_cnt <= f_cnt+1'b1;
if( f_cnt>=f_cnt3 ) //循環復位
f_cnt <= 28'd0;
end
else f_cnt <= 28'd0;
end
always@( posedge sclk or posedge f_cs1 or posedge f_cs2 ) begin
if ( f_cs1 ) begin
case ( f_cnt )
f0: Fout1 <= 1'b1;
f1: Fout2 <= 1'b1;
f2: Fout1 <= 1'b0;
f3: Fout2 <= 1'b0;
endcase
end
else begin
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
if ( f_cs2 ) begin
case(f_cnt)
f4: Fout3 <= 1'b1;
f5: Fout4 <= 1'b1;
f6: Fout3 <= 1'b0;
f7: Fout4 <= 1'b0;
endcase
if(f_cnt1>=f_cnt2) begin
if(f_cnt==f8)begin
Fout4 <= 1'b0;
end
end
end
else begin
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
end
endmodule
*/
/*
//IGBT 波形發生 2個通道
module PFMc ( sclk, f_en1,f_en2,f_i,Ts_i,Fout1, Fout2 ,Fout3, Fout4);
input sclk ; //晶振50M 20ns
input f_en1; //波形輸出封鎖信號 0封鎖輸出
input f_en2; //波形輸出封鎖信號 0封鎖輸出
input [17:1] f_i; //PWM頻率 Hz 最小1HZ,最大40K
input [6:1]Ts_i; //PWM周期 us 最大25
output reg Fout1 ; //通道1PWM輸出
output reg Fout2 ;
output reg Fout3 ; //通道2PWM輸出
output reg Fout4 ;
reg f_cs1 = 1'd0; //通道1波形使能
reg f_cs2 = 1'd0; //通道2波形使能
reg [28:1] f_cnt = 0 ;
reg [12:1] f_cnt1 = 0 ; //Ts高電平計數個數
reg [26:1] f_cnt2 = 250 ; //Ts 低電平計數個數
reg [28:1] f_cnt3 ;
reg f0 = 1'd0;
reg [12:1] f1=0;
reg [27:1] f2=0,f3=0;
reg [28:1] f4=0,f5=0;
reg [28:1] f6=0,f7=0;
reg [12:1] f8=0;
reg [17:1] f_buffer=0;
reg [6:1]Ts_buffer=0;
reg [17:1] f=40000;
reg [6:1]Ts=0;
always @( posedge sclk ) begin //TS f參數緩存1個周期，在1個周期完后生效
if( f_cnt == 0 ) begin
f_buffer <= f_i;
Ts_buffer <= Ts_i;
end
if( f_cnt1 < f_cnt2 ) begin
if(f_cnt == f_cnt3) begin
f<=f_buffer;
Ts<=Ts_buffer;
end
end
if( f_cnt1 >= f_cnt2 ) begin
if(f_cnt == f8) begin
f<=f_buffer;
Ts<=Ts_buffer;
end
end
end
always @( Ts or f ) begin //參數設置改變后，對參數初始化
f_cnt1 = Ts*50 ; //(Ts*1000)/20; //Ts高電平計數個數
f_cnt2 = (1000000/f)*25; //對應1/2 f個周期計數個數
f_cnt3 = (1000000/f)*25<<2 ; //4個驅動方波輸出周期
f0 = 1 'd0; //4個電平翻轉狀態 PFM1上升沿
f1 = Ts*50; //PFM1 下降沿
f2 = (1000000/f)*25<<1 ; //PFM2上升沿
f3= {(1000000/f)*25<<1}+Ts*50; //PFM2 下降沿
f4 =(1000000/f)*25; //PFM3上升沿
f5 =(1000000/f)*25+Ts*50; //PFM3 下降沿
f6 = {(1000000/f)*25<<1}+(1000000/f)*25; //PFM4上升沿
f7 = {(1000000/f)*25<<1}+{(1000000/f)*25}+Ts*50; //PFM4 下降沿
f8 = Ts*50-(1000000/f)*25;
end
always@( posedge sclk ) begin //波形輸出期間，禁止關斷
if( Fout1 || Fout2 )
f_cs1 <= 1'd1 ;
else f_cs1 <=f_en1 ;
if( Fout3 || Fout4 )
f_cs2 <= 1'd1 ;
else f_cs2 <=f_en2 ;
end
always@( posedge sclk or posedge f_cs1 or posedge f_cs2 ) begin //通道1 2循環
if( f_cs1 || f_cs2 ) begin //使能
f_cnt <= f_cnt+1;
if( f_cnt>=f_cnt3 ) //循環復位
f_cnt <= 0;
end
else f_cnt <= 0;
end
always@( posedge sclk or posedge f_cs1 or posedge f_cs2) begin
if ( f_cs1 ) begin
if(f_cnt==f0)begin
Fout1 <= 1'b1;
// Fout2 <= 1'b0;
end
if(f_cnt==f1)begin
Fout1 <= 1'b0;
// Fout2 <= 1'b0;
end
if(f_cnt==f2)begin
// Fout1 <= 1'b0;
Fout2 <= 1'b1;
end
if(f_cnt==f3)begin
// Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
end
else begin
Fout1 <= 1'b0;
Fout2 <= 1'b0;
end
if ( f_cs2 ) begin
if(f_cnt==f4)begin
Fout3 <= 1'b1;
end
if(f_cnt==f5)begin
Fout3 <= 1'b0;
end
if(f_cnt==f6)begin
Fout4 <= 1'b1;
end
if(f_cnt==f7)begin
Fout4 <= 1'b0;
end
if(f_cnt1>=f_cnt2) begin
if(f_cnt==f8)begin
Fout4 <= 1'b0;
end
end
end
else begin
Fout3 <= 1'b0;
Fout4 <= 1'b0;
end
end
endmodule、
*/
/*
module PFMc ( sclk, f_en1,f_en2,f_i,Ts_i,Fout1, Fout2 ,Fout3, Fout4);
input sclk ; //晶振50M 20ns
input f_en1; //波形輸出封鎖信號 0封鎖輸出
input f_en2; //波形輸出封鎖信號 0封鎖輸出
input [18:1] f_i; //PWM頻率 Hz 最小1HZ,最大40K
input [6:1]Ts_i; //PWM周期 us 最大25
output reg Fout1 = 1'b0 ; //通道1PWM輸出
output reg Fout2 = 1'b0 ;
output reg Fout3 = 1'b0 ; //通道2PWM輸出
output reg Fout4 = 1'b0 ;
reg f_cs1 = 1'd0; //通道1波形使能
reg f_cs2 = 1'd0; //通道2波形使能
reg [28:1] f_cnt = 0 ;
reg [12:1] f_cnt1 = 0 ; //Ts高電平計數個數
reg [26:1] f_cnt2 = 250 ; //Ts 低電平計數個數
reg [26:1] f_cnt3 ;
reg f0 = 1'd0;
reg [12:1] f1=0;
reg [27:1] f2=0,f3=0;
reg [28:1] f4=0,f5=0;
reg [28:1] f6=0,f7=0;
reg [12:1] f8=0;
reg [4:1] state; //狀態指示
reg spr=1'b0; //參數計算完成指示
reg [18:1] f_ib; //PWM頻率 Hz 最小1HZ,最大40K 緩存
reg [6:1]Ts_ib; //PWM周期 us 最大25 緩存
reg [18:1] f=40000; //PWM頻率 Hz 最小1HZ,最大40K 緩存
reg [6:1]Ts=0; //PWM周期 us 最大25 緩存
parameter
Fout1_start = 4'd0,
Fout2_start = 4'd1,
Fout1_end = 4'd2,
Fout2_end = 4'd3,
Fout3_start = 4'd4,
Fout4_start = 4'd5,
Fout3_end = 4'd6,
Fout4_end = 4'd7,
Fout_clear = 4'd8;
always @( Ts or f ) begin //參數設置改變后，對參數初始化
f_cnt1 = Ts*50 ; //(Ts*1000)/20; //Ts高電平計數個數
f_cnt2 = (1000000/f)*25; //對應1/2 f個周期計數個數
f_cnt3 = (1000000/f)*25<<2 ; //4個驅動方波輸出周期
f0 = 1 'd0; //4個電平翻轉狀態 PFM1上升沿
f1 = Ts*50; //PFM1 下降沿
f2 = (1000000/f)*25<<1 ; //PFM2上升沿
f3= {(1000000/f)*25<<1}+Ts*50; //PFM2 下降沿
f4 =(1000000/f)*25; //PFM3上升沿
f5 =(1000000/f)*25+Ts*50; //PFM3 下降沿
f6 = {(1000000/f)*25<<1}+(1000000/f)*25; //PFM4上升沿
f7 = {(1000000/f)*25<<1}+{(1000000/f)*25}+Ts*50; //PFM4 下降沿
f8 = Ts*50-(1000000/f)*25;
end
always@( f_en1 or f_en2) begin //波形輸出期間，禁止關斷
if( Fout1 || Fout2 )
f_cs1 <= 1'd1 ;
else f_cs1 <=f_en1 ;
if( Fout3 || Fout4 )
f_cs2 <= 1'd1 ;
else f_cs2 <=f_en2 ;
end
always@( f_cnt ) begin
if( f_cnt ) begin
f_ib = f_i;
Ts_ib = Ts_i;
end
if( (f_cnt+1)== f_cnt3) begin
f = f_ib;
Ts = Ts_ib;
end
end
always@( posedge sclk ) begin //通道1 2循環
if( f_cs1 || f_cs2 ) begin //使能
f_cnt <= f_cnt+1;
spr <= ~spr;
if( f_cnt>=f_cnt3 ) //循環復位
f_cnt <= 0;
end
else f_cnt <= 0;
end
always@( posedge sclk ) begin
if ( f_cs1 ) begin
if(f_cnt==f0)begin
state <= Fout1_start;
end
if(f_cnt==f1)begin
state <= Fout2_start;
// Fout2 <= 1'b0;
end
if(f_cnt==f2)begin
// Fout1 <= 1'b0;
state <= Fout1_end;
end
if(f_cnt==f3)begin
// Fout1 <= 1'b0;
state <= Fout2_end;
end
end
else state <= Fout_clear;
if ( f_cs2 ) begin
if(f_cnt==f4)begin
state <= Fout3_start;;
end
if(f_cnt==f5)begin
state <= Fout4_start;;
end
if(f_cnt==f6)begin
state <= Fout3_end;
end
if(f_cnt==f7)begin
state <= Fout4_end;
end
if(f_cnt1>=f_cnt2) begin
if(f_cnt==f8)begin
state <= Fout4_end;
end
end
end
else state <= Fout_clear;
end
always@( state ) begin
case (state)
Fout1_start: begin
Fout1 = 1'b1;
Fout2 = 1'b0;
end
Fout2_start: begin
Fout2 = 1'b1;
Fout1 = 1'b1;
end
Fout3_start: begin
Fout3 = 1'b1;
Fout4 = 1'b0;
end
Fout4_start: begin
Fout4 = 1'b1;
Fout3 = 1'b0;
end
Fout1_end : begin
Fout1 = 1'b0;
Fout2 = 1'b1;
end
Fout2_end : begin
Fout2 = 1'b0;
Fout1 = 1'b0;
end
Fout3_end : begin
Fout3 = 1'b0;
Fout4 = 1'b1;
end
Fout4_end : begin
Fout3 = 1'b0;
Fout4 = 1'b0;
end
Fout_clear : begin
Fout1 = 1'b0;
Fout2 = 1'b0;
Fout1 = 1'b0;
Fout1 = 1'b0;
end
default begin
Fout1 = 1'b0;
Fout2 = 1'b0;
Fout1 = 1'b0;
Fout1 = 1'b0;
end
endcase
end
endmodule
*/

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