fpga SPI接口源代碼

ID:581831 · 發表于 2020-10-24 10:29

FPGA與SPI接口程序(hdl源代碼)

`timescale 1ns/1ps
module spi(clk,reset,mosi,sclk,csb);
input clk;
input reset;
//input enable;
output mosi;
output sclk;
output csb;
reg sclk_reg;
reg csb;
reg [7:0] counter;
reg [4:0] mosi_index;
wire clk_s;
parameter enable = 1'b1;
parameter spi_data = 16'h8000;
// Instantiate the module
clk_gen instance_name (
.clk(clk),
.reset(reset),
.clk_o(clk_s)
);
//generate fl counter
always@ (posedge clk_s or negedge reset)
begin
if(!reset)
counter <= 8'b0;
else if(enable)
begin
if(counter< 8'h35)
counter <= counter + 1;
end
end
//generate signal csb
always@ (posedge clk_s or negedge reset)
begin
if(!reset)
csb <= 1'b1;
else if(counter>= 8'b1 && counter<= 8'h32)
csb <= 1'b0;
else
csb <= 1'b1;
end
//Generate sclk
always@ (posedge clk_s)
begin
case(counter)
8'h02: sclk_reg <= 1'b1;
8'h05: sclk_reg <= 1'b1;
8'h08: sclk_reg <= 1'b1;
8'h0b: sclk_reg <= 1'b1;
8'h0e: sclk_reg <= 1'b1;
8'h11: sclk_reg <= 1'b1;
8'h14: sclk_reg <= 1'b1;
8'h17: sclk_reg <= 1'b1;
8'h1a: sclk_reg <= 1'b1;
8'h1d: sclk_reg <= 1'b1;
8'h20: sclk_reg <= 1'b1;
8'h23: sclk_reg <= 1'b1;
8'h26: sclk_reg <= 1'b1;
8'h29: sclk_reg <= 1'b1;
8'h2c: sclk_reg <= 1'b1;
8'h2f: sclk_reg <= 1'b1;
default: sclk_reg <= 1'b0;
endcase
end
always@ (counter or csb)
begin
if(csb == 0)
case(counter)
8'h00,
8'h01,
8'h02,
8'h03: mosi_index = 5'h0F;
8'h04,
8'h05,
8'h06: mosi_index = 5'h0E;
8'h07,
8'h08,
8'h09: mosi_index = 5'h0D;
8'h0A,
8'h0B,
8'h0C: mosi_index = 5'h0C;
8'h0D,
8'h0E,
8'h0F: mosi_index = 5'h0B;
8'h10,
8'h11,
8'h12: mosi_index = 5'h0A;
8'h13,
8'h14,
8'h15: mosi_index = 5'h09;
8'h16,
8'h17,
8'h18: mosi_index = 5'h08;
8'h19,
8'h1A,
8'h1B: mosi_index = 5'h07;
8'h1C,
8'h1D,
8'h1E: mosi_index = 5'h06;
8'h1F,
8'h20,
8'h21: mosi_index = 5'h05 ;
8'h22,
8'h23,
8'h24: mosi_index = 5'h04;
8'h25,
8'h26,
8'h27: mosi_index = 5'h03 ;
8'h28,
8'h29,
8'h2A: mosi_index = 5'h02 ;
8'h2B,
8'h2C,
8'h2D: mosi_index = 5'h01;
8'h2E,
8'h2F,
8'h30: mosi_index = 5'h00;
default: mosi_index = 5'h00;
endcase
else mosi_index = 8'h00;
end
assign sclk = sclk_reg;
assign mosi = spi_data[mosi_index];
endmodule

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fpga SPI接口源代碼

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