FPGA Verilog呼吸燈程序

ID:471101 · 發表于 2019-11-8 14:26

Verilog程序，實現LED逐漸變亮逐漸變暗功能

/*-----------------------------------------------------------
filename:Breath_led.v
Author: Terry
Data:2019-02-17
Version:0.1
Description: ??????
----------------------------------------------------------------*/
module Breath_led (
input wire sys_clk,
input wire reset,
output reg [3:0]one_led,
output reg o_1Mhz );
parameter END_CNT1=99,
END_CNT2=999,
END_CNT3=999;
reg [6:0] count_1Mhz; //49
reg [10:0] count_1Khz; //999
reg [10:0] count_1hz; //999
reg flag_1khz;
reg flag_state;
// 0-49???????
always @(posedge sys_clk or negedge reset )
if (reset==0)
count_1Mhz <= 0;
else if(count_1Mhz==END_CNT1)
count_1Mhz <= 0;
else
count_1Mhz <= count_1Mhz+1;
// 1MHZ???????? ?????????????????????
always @(posedge sys_clk or negedge reset )
if (reset==0)
o_1Mhz <= 0;
else if(count_1Mhz==END_CNT1)
o_1Mhz <= 1;
else
o_1Mhz <= 0;
// ??1MHZ???м??? 1000??
always @(posedge sys_clk or negedge reset )
if (reset==0)
count_1Khz <= 0;
else if((o_1Mhz==1)&&(count_1Khz==END_CNT2))
begin
count_1Khz <= 0;
flag_1khz <= 1;
end
else if(o_1Mhz==1)
count_1Khz <= count_1Khz+1;
else
begin
count_1Khz <= count_1Khz;
flag_1khz <= 0;
end
// ??flag_1khz???????м??? 1000??
always @(posedge sys_clk or negedge reset )
if (reset==0)
begin
count_1hz <= 0;
flag_state <=0;
end
else if((flag_1khz==1)&&(count_1hz==END_CNT3))
begin
count_1hz <= 0;
flag_state <=~flag_state;
end
else if(flag_1khz==1)
count_1hz <= count_1hz+1;
else
begin
count_1hz <= count_1hz;
// flag_1khz <= 0; //同一個寄存器在兩個always中賦值會出錯
end
// ??????
always @(posedge sys_clk or negedge reset )
if (reset==0)
one_led <= 0;
else if ((count_1Khz>count_1hz)&&(flag_state==1))
one_led <=4'b1111 ;
else if ((count_1Khz>count_1hz)&&(flag_state==0))
one_led <=4'b0000 ;
else if ((count_1Khz<=count_1hz)&&(flag_state==1))
one_led <=4'b0000;
else if ((count_1Khz<=count_1hz)&&(flag_state==0))
one_led <=4'b1111 ;
else
one_led<=one_led;
endmodule

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FPGA Verilog呼吸燈程序

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