verilog實現冒泡排序源程序

ID:631487 · 發表于 2019-10-28 16:28

使用veriog實現冒泡排序

verilog源程序如下:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:16:46 03/30/2018
// Design Name:
// Module Name: mian
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//=============================== 說明 =====================================
// 按照地址從小往大遞增的順序，數據是從大到小排列
//================================================================================
module main#(
parameter ROW_WIDTH = 8, //行
parameter COL_WIDTH = 16 //列
)
(
input clk,
input rst,
input enable
);
//--------------------------------------------------------------------------------
reg [15:0] comp_data_i; //數據
reg valid_i; //數據有效
reg [15:0] data [COL_WIDTH:1];
reg [7:0] count;
//--------------------------------------------------------------------------------
initial
begin
data[1] = 16'd20;
// data[2] = 16'd723;
data[2] = 16'd20;
data[3] = 16'd12;
data[4] = 16'd456;
data[5] = 16'd278;
data[6] = 16'd9756;
data[7] = 16'd433;
data[8] = 16'd10000;
data[9] = 16'd21;
data[10] = 16'd724;
data[11] = 16'd15;
data[12] = 16'd458;
data[13] = 16'd279;
data[14] = 16'd9758;
data[15] = 16'd439;
data[16] = 16'd30;
end
//--------------------------------------------------------------------------------
always@(posedge clk or posedge rst)
begin
if(rst)
begin
count <= COL_WIDTH + 1;
valid_i <= 0;
comp_data_i <= 0;
end
else if(enable)
begin
count <= 1;
end
else if(count <= COL_WIDTH)
begin
comp_data_i <= data[count];
count <= count + 1;
valid_i <= 1;
end
else
begin
valid_i <= 0;
count <= count;
end
end
//--------------------------------------------------------------------------------
// 并行比較排序算法
//--------------------------------------------------------------------------------
parallel u0_parallel (
.clk ( clk ),
.rst ( rst ),
.comp_data_i ( comp_data_i ),
.valid_i ( valid_i )
);
//--------------------------------------------------------------------------------
// 串行比較排序算法
//--------------------------------------------------------------------------------
serial u1_serial (
.clk ( clk ),
.rst ( rst ),
.comp_data_i ( comp_data_i ),
.valid_i ( valid_i )
);
//--------------------------------------------------------------------------------
// 冒泡法
//--------------------------------------------------------------------------------
bubbling u2_bubbling (
.clk ( clk ),
.rst ( rst ),
.comp_data_i ( comp_data_i ),
.valid_i ( valid_i )
);
//--------------------------------------------------------------------------------
endmodule

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verilog實現冒泡排序源程序

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