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本人做的一些eda代碼,如果有需要可以下載
- 半加器代碼
- ENTITY lytadder5091 IS
- PORT(A, B:IN bit;
- C, Sum:OUT bit);
- END ENTITY lytadder5091;
- ARCHITECTURE rtl of lytadder5091 is
- begin
- Sum<=(A XOR B);
- C<=(A AND B);
- END ARCHITECTURE rtl;
- 全加器代碼
- ENTITY quanjiaqi5091 IS
- PORT(A, B, D:IN bit;
- C, Sum:OUT bit);
- END ENTITY quanjiaqi5091;
- ARCHITECTURE rtl of quanjiaqi5091 is
- begin
- Sum<=A XOR B XOR D;
- C<=(A AND B)OR(A AND D)OR(D AND B);
- END ARCHITECTURE rtl;
- 三人表決器代碼(一燈)
- ENTITY SRBJQ5091 IS
- PORT(A, B,C:IN bit;
- JIEGUO:OUT bit);
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- JIEGUO<=(A AND B)OR(A AND C)OR(C AND B);
-
- END ARCHITECTURE rtl;
- 三人表決器代碼(8燈)
- ENTITY SRBJQ5091 IS
- PORT(A, B,C:IN bit;
- D0,D1,D2,D3,D4,D5,D6,D7:OUT bit);
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- D0<=(A AND B)OR(A AND C)OR(C AND B);
- D1<=(A AND B)OR(A AND C)OR(C AND B);
- D2<=(A AND B)OR(A AND C)OR(C AND B);
- D3<=(A AND B)OR(A AND C)OR(C AND B);
- D4<=(A AND B)OR(A AND C)OR(C AND B);
- D5<=(A AND B)OR(A AND C)OR(C AND B);
- D6<=(A AND B)OR(A AND C)OR(C AND B);
- D7<=(A AND B)OR(A AND C)OR(C AND B);
-
- END ARCHITECTURE rtl;
- 三人表決器(1燈)
- ENTITY SRBJQ5091 IS
- PORT(A, B,C:IN bit;
- D:OUT bit);
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- cale:process(A,B,C)
- VARIABLE TMP1,TMP2,TMP3,TMP4:BIT;
- BEGIN
- TMP1:=A AND B;
- TMP2:=A AND C;
- TMP3:=B AND c;
- TMP4:=TMP1 OR TMP2 OR TMP3;
- d<=tmp4;
- END PROCESS;
-
-
- END ARCHITECTURE rtl;
- 三人表決器(8燈)
- ENTITY SRBJQ5091 IS
- PORT(A, B,C:IN bit;
- D:OUT bit_VECTOR(0 TO 7));
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- cale:process(A,B,C)
- VARIABLE TMP1,TMP2,TMP3,TMP4:BIT;
- BEGIN
- TMP1:=A AND B;
- TMP2:=A AND C;
- TMP3:=B AND c;
- TMP4:=TMP1 OR TMP2 OR TMP3;
- d(0)<=tmp4;d(1)<=tmp4;
- d(2)<=tmp4;d(3)<=tmp4;
- d(4)<=tmp4;d(5)<=tmp4;
- d(6)<=tmp4;d(7)<=tmp4;
- END PROCESS;
-
-
- END ARCHITECTURE rtl;
- 三人表決器
- ENTITY SRBJQ5091 IS
- PORT(A, B,C:IN bit;
- D:OUT bit_vector(0 to 7));
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- cale:process(A,B,C)
- BEGIN
- if ((A AND B)OR(A AND C)OR(C AND B))='0'
- then d<="00000000";
- else d<="11111111";
- end if;
-
- END PROCESS;
-
-
- END ARCHITECTURE rtl;
- 四人表決器
- ENTITY SRBJQ5091 IS
- PORT(A, B,C,E:IN bit;
- D:OUT bit_vector(0 to 7));
- END ENTITY SRBJQ5091;
- ARCHITECTURE rtl of SRBJQ5091 is
- begin
- cale:process(A,B,C,E)
- BEGIN
- if ((A AND B)OR(A AND E)OR(C AND A))='1'
- then d<="00000000";
- else d<="11111111";
- end if;
-
- END PROCESS;
-
-
- END ARCHITECTURE rtl;
- 七段譯碼器
- -
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- ENTITY QIDUANYIMAQI IS
- PORT(bcdin : IN std_logic_vector(3 DOWNTO 0);
- segout : OUT std_logic_vector(6 DOWNTO 0);
- T : OUT BIT);
- END QIDUANYIMAQI;
- ARCHITECTURE ver3 OF QIDUANYIMAQI IS
- BEGIN
- T<='0';
- WITH bcdin SELECT
- segout <= "0000001" WHEN X"0",
- "1001111" WHEN X"1",
-
- "0010010" WHEN X"2",
- "0000110" WHEN X"3",
- "1001100" WHEN X"4",
- "0100100" WHEN X"5",
- "0100000" WHEN X"6",
- "0001111" WHEN X"7",
- "0000000" WHEN X"8",
- "0000100" WHEN X"9",
- "1111111" WHEN OTHERS;
- END ver3;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity xue is
- port (
- clkin:in std_logic;
- clkout:out std_logic_vector(7 downto 0);
- enout:out std_logic_vector(3 downto 0)
- );
- end entity;
- architecture behave of xue is
- signal mtime:std_logic_vector(15 downto 0);
- signal me:std_logic_vector(1 downto 0);
- signal m7_0:std_logic_vector(7 downto 0);
- signal m7_1:std_logic_vector(7 downto 0);
- signal m7_2:std_logic_vector(7 downto 0);
- signal m7_3:std_logic_vector(7 downto 0);
- begin
- process(clkin)
- begin
- if(clkin'event and clkin='1')then
- mtime<=mtime+1;
- if(mtime="1000000000000000")then
- mtime<=(others=>'0');
- if(me="11")then
- me<=(others=>'0');
- else
- me<=me+1;
- end if;
- end if;
- m7_0<="10011110";
- m7_1<="00001000";
- m7_2<="00000010";
- m7_3<="01001000";
- if(me="00")then
- enout<="1110";
- clkout<=m7_0;
- end if;
- if(me="01")then
- enout<="1101";
- clkout<=m7_1;
- end if;
- if(me="10")then
- enout<="1011";
- clkout<=m7_2;
- end if;
- if(me="11")then
- enout<="0111";
- clkout<=m7_3;
- end if;
- end if;
- end process;
- end behave;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity xue is
- port (c:in bit;
- clkin:in std_logic;
- clkout:out std_logic_vector(7 downto 0);
- enout:out std_logic_vector(3 downto 0)
- );
- end entity;
- architecture behave of xue is
- signal mtime:std_logic_vector(15 downto 0);
- signal me:std_logic_vector(1 downto 0);
- signal m7_0:std_logic_vector(7 downto 0);
- signal m7_1:std_logic_vector(7 downto 0);
- signal m7_2:std_logic_vector(7 downto 0);
- signal m7_3:std_logic_vector(7 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- begin
- process(clkin,c)
- begin
- if(clkin'event and clkin='1')then
- mtime<=mtime+1;
- if(mtime="1000000000000000")then
- mtime<=(others=>'0');
- if(me="11")then
- me<=(others=>'0');
- else
- me<=me+1;
- end if;
- end if;
- m7_0<="10011110";
- m7_1<="00001000";
- m7_2<="00000010";
- m7_3<="01001000";
- m0<="00011110";
- m1<="00000010";
- m2<="10011110";
- m3<="00100100";
- if(me="00"and c='1')then
- enout<="1110";
- clkout<=m7_0;
- end if;
- if(me="001"and c='1')then
- enout<="1101";
- clkout<=m7_1;
- end if;
- if(me="010"and c='1')then
- enout<="1011";
- clkout<=m7_2;
- end if;
- if(me="011"and c='1')then
- enout<="0111";
- clkout<=m7_3;
- end if;
- if(me="000"and c='0')then
- enout<="1110";
- clkout<=m0;
- end if;
- if(me="001"and c='0')then
- enout<="1101";
- clkout<=m1;
- end if;
- if(me="010"and c='0')then
- enout<="1011";
- clkout<=m2;
- end if;
- if(me="011"and c='0')then
- enout<="0111";
- clkout<=m3;
- end if;
- end if;
- end process;
- end behave;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity qiduanyimaqi5091 is
- port (
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- led1_4:out std_logic_vector(3 downto 0)--選擇觸發的
- );
- end entity qiduanyimaqi5091;
- architecture lyt of qiduanyimaqi5091 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- begin
- process(clk)
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- if(clk1="1000000000000000")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="011")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011111";
- m2<="00100101";
- m3<="00001101";
- m4<="10011001";--儲存十個不同數字
- m5<="01001001";
- m6<="01000001";
- m7<="00011111";
- m8<="00000001";
- m9<="00001001";
- if(clk2="000")then
- led1_4<="0111";
- led<=m5;
- end if;
- if(clk2="001")then
- led1_4<="1011";
- led<=m0; --賦值
- end if;
- if(clk2="010")then
- led1_4<="1101";
- led<=m9;
- end if;
- if(clk2="011")then
- led1_4<="1110";
- led<=m1;
- end if;
- end if;
- end process;
- end lyt;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity qiduanyimaqi15091 is
- port (c:in bit;--控制顯示數字
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end qiduanyimaqi15091;
- architecture lyt of qiduanyimaqi15091 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- begin
- process(clk)
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- if(clk1="1111111111111111")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="111")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- m0<="00000010";
- m1<="10011111";
- m2<="00100101";
- m3<="00001101";
- m4<="10011001";--儲存十個不同數字
- m5<="01001001";
- m6<="01000001";
- m7<="00011111";
- m8<="00000001";
- m9<="00001001";
- if(clk2="000"and c='0')then
- led1_4<="0111";
- led<=m2;
- end if;
- if(clk2="001"and c='0')then
- led1_4<="1011";
- led<=m0; --賦值
- end if;
- if(clk2="010"and c='0')then
- led1_4<="1101";
- led<=m1;
- end if;
- if(clk2="011"and c='0')then
- led1_4<="1110";
- led<=m7;
- end if;
- if(clk2="100"and c='1')then
- led1_4<="0111";
- led<=m5;
- end if;
- if(clk2="101"and c='1')then
- led1_4<="1011";
- led<=m0;
- end if;
- if(clk2="110"and c='1')then
- led1_4<="1101";
- led<=m9;
- end if;
- if(clk2="111"and c='1')then
- led1_4<="1110";
- led<=m1;
- end if;
- end if;
- end process;
- end lyt;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity shiyan3 is
- port (K1,K2,K3:in bit;--控制顯示數字
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- STAR:out std_logic_vector(7 downto 0);--二極管
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end shiyan3;
- architecture lyt of shiyan3 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal clk3:std_logic_vector(25 downto 0);
- signal clk4:std_logic_vector(3 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- signal N0:std_logic_vector(7 downto 0);
- signal N1:std_logic_vector(7 downto 0);
- signal N2:std_logic_vector(7 downto 0);
- signal N3:std_logic_vector(7 downto 0);
- signal N4:std_logic_vector(7 downto 0);
- signal N5:std_logic_vector(7 downto 0);
- signal L0:std_logic_vector(7 downto 0);
- signal L1:std_logic_vector(7 downto 0);
- signal L2:std_logic_vector(7 downto 0);
- signal L3:std_logic_vector(7 downto 0);
- signal L4:std_logic_vector(7 downto 0);
- begin
- P1:process(clk,K1)---控制七段顯示學號的進程
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- clk3<=clk3+1;
- if(clk1="1111111111111111")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="011")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- if(clk3="10111110101111000010000000")then
- clk3<=(others=>'0'); ---時鐘控制
- if(clk4="1001")then
- clk4<=(others=>'0');
- else
- clk4<=clk4+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011110";
- m2<="00100100";
- m3<="00001100";
- m4<="10011000";--儲存十個不同led數字
- m5<="01001000";
- m6<="01000000";
- m7<="00011110";
- m8<="00000000";
- m9<="00001000";
- if(clk2="0000"and K1='1')then
- led1_4<="0111";
- led<=m5;
- end if;
- if(clk2="0001"and K1='1')then
- led1_4<="1011";
- led<=m0; --賦值
- end if;
- if(clk2="0010"and K1='1')then
- led1_4<="1101";
- led<=m9;
- end if;
- if(clk2="0011"and K1='1')then
- led1_4<="1110";
- led<=m1;
- end if;
- if(K1='0')then
- led1_4<="1111";
- led<=m1;
- end if;
-
- end if;
- end process P1;
- P2:process(clk4,K1)--控制流水燈模式1的進程
- begin
- N0<="00011111";
- N1<="10001111";
- N2<="11000111";
- N3<="11100011";
- N4<="11110001";--儲存六個第一種二極管信號
- N5<="11111000";
- if(k1 and k2 and k3)='1' then
- star<="11111111" ;
- end if;
- if(clk4="0000"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N0;
- end if;
- if(clk4="0001"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N1;
- end if;
- if(clk4="0010"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N2;
- end if;
- if(clk4="0011"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N3;
- end if;
- if(clk4="0100"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N4;
- end if;
- if(clk4="0101"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N5;
- end if;
- if(clk4="0110"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N4;
- end if;
- if(clk4="0111"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N3;
- end if;
- if(clk4="1000"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N2;
- end if;
- if(clk4="1001"and ((K1 AND(K2 XOR K3))OR(NOT K1 AND K2 AND K3))='1')then
- STAR<=N1;
- end if;
- end process P2;
- ---P3:process(clk4,K2)--控制流水燈模式2的進程
- --begin
- -- L0<="11100111";
- -- L1<="11010011";
- --L2<="10111101";
- -- L3<="01111110";
- -- L4<="11111111";--儲存五個第二種二極管信號
- -- if(clk4="0000"and K1='0'and k2='0'and k3='1')then
- --STAR<=L0;
- -- end if;
- --if(clk4="0001"and K1='0'and k2='0'and k3='1')then
- -- STAR<=L1;
- --end if;
- --if(clk4="0010"and K1='0'and k2='0'and k3='1')then
- --STAR<=L2;
- --end if;
- -- if(clk4="0011"and K1='0'and k2='0'and k3='1')then
- --STAR<=L3;
- -- end if;
- -- if(clk4="0100"and K1='0'and k2='0'and k3='1')then
- -- STAR<=L4;
- -- end if;
- -- end process P3;
- end lytlibrary ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity shiyan3 is
- port (K1,K2,K3:in bit;--控制顯示數字
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- STAR:out std_logic_vector(7 downto 0);--二極管
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end shiyan3;
- architecture lyt of shiyan3 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal clk3:std_logic_vector(25 downto 0);
- signal clk4:std_logic_vector(3 downto 0);
- signal clk5:std_logic_vector(2 downto 0);
- signal clk6:std_logic_vector(1 downto 0);
- signal A:std_logic_vector(2 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- signal N0:std_logic_vector(7 downto 0);
- signal N1:std_logic_vector(7 downto 0);
- signal N2:std_logic_vector(7 downto 0);
- signal N3:std_logic_vector(7 downto 0);
- signal N4:std_logic_vector(7 downto 0);
- signal N5:std_logic_vector(7 downto 0);
- signal L0:std_logic_vector(7 downto 0);
- signal L1:std_logic_vector(7 downto 0);
- signal L2:std_logic_vector(7 downto 0);
- signal L3:std_logic_vector(7 downto 0);
- signal L4:std_logic_vector(7 downto 0);
- signal T0:std_logic_vector(7 downto 0);
- signal T1:std_logic_vector(7 downto 0);
- begin
- P1:process(clk,K1)---控制七段顯示學號的進程
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- clk3<=clk3+1;
- if(clk1="1111111111111111")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="011")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- if(clk3="10111110101111000010000000")then
- clk3<=(others=>'0'); ---時鐘控制
- if(clk4="1010")then
- clk4<=(others=>'0');
- else
- clk4<=clk4+1;
- end if;
- if(clk5="100")then
- clk5<=(others=>'0');
- else
- clk5<=clk5+1;
- end if;
- if(clk6="01")then
- clk6<=(others=>'0');
- else
- clk6<=clk6+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011110";
- m2<="00100100";
- m3<="00001100";
- m4<="10011000";--儲存十個不同led數字
- m5<="01001000";
- m6<="01000000";
- m7<="00011110";
- m8<="00000000";
- m9<="00001000";
- if(clk2="0000"and K1='1')then
- led1_4<="0111";
- led<=m5;
- end if;
- if(clk2="0001"and K1='1')then
- led1_4<="1011";
- led<=m0; --賦值
- end if;
- if(clk2="0010"and K1='1')then
- led1_4<="1101";
- led<=m9;
- end if;
- if(clk2="0011"and K1='1')then
- led1_4<="1110";
- led<=m1;
- end if;
- if(K1='0')then
- led1_4<="1111";
- led<=m1;
- end if;
-
- end if;
- end process P1;
- P2:process(clk4,K1)--控制流水燈的進程
- begin N0<="00011111";
- N1<="10001111";
- N2<="11000111";
- N3<="11100011";
- N4<="11110001";--儲存六個第一模式二極管信號
- N5<="11111000";
- L0<="11100111";
- L1<="11011011";
- L2<="10111101";
- L3<="01111110";
- L4<="11111111";--儲存五個第二模式二極管信號
- T0<="01010101";
- T1<="10101010";--儲存二個第三模式二極管信號
- if(k1 and k2 and k3)='1' then
- star<="11111111" ;
- - end if;
- if(clk4="0001"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N0;
- end if;
- if(clk4="0010"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N1;
- end if;
- if(clk4="0011"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N2;
- end if;
- if(clk4="0100"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N3;
- end if;
- if(clk4="0101"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N4;
- end if;
- if(clk4="0110"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N5;
- end if;
- if(clk4="0111"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N4;
- end if;
- if(clk4="1000"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N3;
- end if;
- if(clk4="1001"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N2;
- end if;
- if(clk4="1010"and K1='0'AND K2='1'AND K3='1')then
- STAR<=N1;
- end if;
- if(clk5="000"and K1='0'and k2='0'and k3='1')then
- STAR<=L0;
- end if;
- if(clk5="001"and K1='0'and k2='0'and k3='1')then
- STAR<=L1;
- end if;
- if(clk5="010"and K1='0'and k2='0'and k3='1')then
- STAR<=L2;
- end if;
- if(clk5="011"and K1='0'and k2='0'and k3='1')then
- STAR<=L3;
- end if;
- if(clk5="100"and K1='0'and k2='0'and k3='1')then
- STAR<=L4;
- end if;
- if(clk6="00"and K1='0'and k2='1'and k3='0')then
- STAR<=T0;
- end if;
- if(clk6="01"and K1='0'and k2='1'and k3='0')then
- STAR<=T1;
- end if;
- end process P2;
- end lyt;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity shiyan3 is
- port ( A:in BIT_VECTOR(1 TO 3);--控制顯示數字
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- STAR:out std_logic_vector(7 downto 0);--二極管
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end shiyan3;
- architecture lyt of shiyan3 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal clk3:std_logic_vector(25 downto 0);
- signal clk4:std_logic_vector(3 downto 0);
- signal clk5:std_logic_vector(2 downto 0);
- signal clk6:std_logic_vector(1 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- signal N0:std_logic_vector(7 downto 0);
- signal N1:std_logic_vector(7 downto 0);
- signal N2:std_logic_vector(7 downto 0);
- signal N3:std_logic_vector(7 downto 0);
- signal N4:std_logic_vector(7 downto 0);
- signal N5:std_logic_vector(7 downto 0);
- signal L0:std_logic_vector(7 downto 0);
- signal L1:std_logic_vector(7 downto 0);
- signal L2:std_logic_vector(7 downto 0);
- signal L3:std_logic_vector(7 downto 0);
- signal L4:std_logic_vector(7 downto 0);
- signal T0:std_logic_vector(7 downto 0);
- signal T1:std_logic_vector(7 downto 0);
- begin
- P1:process(clk)---控制七段顯示學號的進程
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- clk3<=clk3+1;
- if(clk1="1111111111111111")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="011")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- if(clk3="10111110101111000010000000")then
- clk3<=(others=>'0'); ---時鐘控制
- if(clk4="1010")then
- clk4<="0000";
- else
- clk4<=clk4+1;
- end if;
- if(clk5="100")then
- clk5<=(others=>'0');
- else
- clk5<=clk5+1;
- end if;
- if(clk6="01")then
- clk6<=(others=>'0');
- else
- clk6<=clk6+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011110";
- m2<="00100100";
- m3<="00001100";
- m4<="10011000";--儲存十個不同led數字
- m5<="01001000";
- m6<="01000000";
- m7<="00011110";
- m8<="00000000";
- m9<="00001000";
- if(clk2="0000"and A(1)='1')then
- led1_4<="0111";
- led<=m5;
- end if;
- if(clk2="0001"and A(1)='1')then
- led1_4<="1011";
- led<=m0; --賦值
- end if;
- if(clk2="0010"and A(1)='1')then
- led1_4<="1101";
- led<=m9;
- end if;
- if(clk2="0011"and A(1)='1')then
- led1_4<="1110";
- led<=m1;
- end if;
- if(A(1)='0')then
- led1_4<="1111";
- led<=m1;
- end if;
- end if;
- end process P1;
- P2:process(clk4,CLK5,CLK6)--控制流水燈的進程
- begin
- N0<="00011111";
- N1<="10001111";
- N2<="11000111";
- N3<="11100011";
- N4<="11110001";--儲存六個第一模式二極管信號
- N5<="11111000";
- L0<="11100111";
- L1<="11011011";
- L2<="10111101";
- L3<="01111110";
- L4<="11111111";--儲存五個第二模式二極管信號
- T0<="01010101";
- T1<="10101010";--儲存二個第三模式二極管信號
- if A="111" then
- star<="11111111" ;
- end if;
- if(clk4="0001"and A="011")then
- STAR<=N0;
- end if;
- if(clk4="0010"and A="011")then
- STAR<=N1;
- end if;
- if(clk4="0011"and A="011")then
- STAR<=N2;
- end if;
- if(clk4="0100"and A="011")then
- STAR<=N3;
- end if;
- if(clk4="0101"and A="011")then
- STAR<=N4;
- end if;
- if(clk4="0110"and A="011")then
- STAR<=N5;
- end if;
- if(clk4="0111"and A="011")then
- STAR<=N4;
- end if;
- if(clk4="1000"and A="011")then
- STAR<=N3;
- end if;
- if(clk4="1001"and A="011")then
- STAR<=N2;
- end if;
- if(clk4="1010"and A="011")then
- STAR<=N1;
- end if;
- if(clk5="001"and A="001")then
- STAR<=L0;
- end if;
- if(clk5="010"and A="001")then
- STAR<=L1;
- end if;
- if(clk5="011"and A="001")then
- STAR<=L2;
- end if;
- if(clk5="100"and A="001")then
- STAR<=L3;
- end if;
- if(clk5="101"and A="001")then
- STAR<=L4;
- end if;
- if(clk6="00"and A="010")then
- STAR<=T0;
- end if;
- if(clk6="01"and A="010")then
- STAR<=T1;
- end if;
- end process P2;
- end lyt;
- 最完美代碼
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity shiyan5 is
- port ( A:in BIT_VECTOR(1 TO 3);--控制顯示數字
- clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- STAR:out std_logic_vector(7 downto 0);--二極管
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end shiyan5;
- architecture lyt of shiyan5 is
- signal clk1:std_logic_vector(15 downto 0);
- signal clk2:std_logic_vector(2 downto 0);
- signal clk3:std_logic_vector(25 downto 0);
- signal clk4:std_logic_vector(3 downto 0);
- signal clk5:std_logic_vector(2 downto 0);
- signal clk6:std_logic_vector(1 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- signal N0:std_logic_vector(7 downto 0);
- signal N1:std_logic_vector(7 downto 0);
- signal N2:std_logic_vector(7 downto 0);
- signal N3:std_logic_vector(7 downto 0);
- signal N4:std_logic_vector(7 downto 0);
- signal N5:std_logic_vector(7 downto 0);
- signal L0:std_logic_vector(7 downto 0);
- signal L1:std_logic_vector(7 downto 0);
- signal L2:std_logic_vector(7 downto 0);
- signal L3:std_logic_vector(7 downto 0);
- signal L4:std_logic_vector(7 downto 0);
- signal T0:std_logic_vector(7 downto 0);
- signal T1:std_logic_vector(7 downto 0);
- begin
- P1:process(clk)---控制七段顯示學號的進程
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- clk3<=clk3+1;
- if(clk1="1111111111111111")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk2="011")then
- clk2<=(others=>'0');
- else
- clk2<=clk2+1;
- end if;
- end if;
- if(clk3="10111110101111000010000000")then
- clk3<=(others=>'0'); ---時鐘控制
- if(clk4="1010"and A="011")then
- clk4<="0001";
- elsif(A(1)='1') then
- clk4<="0000";
- else
- clk4<=clk4+1;
- end if;
- if(clk5="101"and A="001")then
- clk5<="001";
- elsif(A(2)='1') THEN clk5<="000";
- ELSE CLK5<=CLK5+1;
- end if;
- if(clk6="10"and A="010")then
- clk6<="01";
- elsif(A(3)='1') THEN clk6<="00";
- ELSE CLK6<=CLK6+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011110";
- m2<="00100100";
- m3<="00001100";
- m4<="10011000";--儲存十個不同led數字
- m5<="01001000";
- m6<="01000000";
- m7<="00011110";
- m8<="00000000";
- m9<="00001000";
- if(clk2="0000"and A(1)='1')then
- led1_4<="0111";
- led<=m5;
- elsif(clk2="0001"and A(1)='1')then
- led1_4<="1011";
- led<=m0; --賦值
- elsif(clk2="0010"and A(1)='1')then
- led1_4<="1101";
- led<=m9;
- elsif(clk2="0011"and A(1)='1')then
- led1_4<="1110";
- led<=m1;
- else led1_4<="1111";
- end if;
- if(A(1)='0')then
- led1_4<="1111";
- end if;
- end if;
- end process P1;
- P2:process(clk4,CLK5,CLK6)--控制流水燈的進程
- begin
- N0<="00011111";
- N1<="10001111";
- N2<="11000111";
- N3<="11100011";
- N4<="11110001";--儲存六個第一模式二極管信號
- N5<="11111000";
- L0<="11100111";
- L1<="11011011";
- L2<="10111101";
- L3<="01111110";
- L4<="11111111";--儲存五個第二模式二極管信號
- T0<="01010101";
- T1<="10101010";--儲存二個第三模式二極管信號
- if A="111" then
- star<="11111111" ;
- end if;
- if(clk4="0001"and A="011")then
- STAR<=N0;
- elsif(clk4="0010"and A="011")then
- STAR<=N1;
- elsif(clk4="0011"and A="011")then
- STAR<=N2;
- elsif(clk4="0100"and A="011")then
- STAR<=N3;
- elsif(clk4="0101"and A="011")then
- STAR<=N4;
- elsif(clk4="0110"and A="011")then
- STAR<=N5;
- elsif(clk4="0111"and A="011")then
- STAR<=N4;
- elsif(clk4="1000"and A="011")then
- STAR<=N3;
- elsif(clk4="1001"and A="011")then
- STAR<=N2;
- elsif(clk4="1010"and A="011")then
- STAR<=N1;
- elsif(clk5="001"and A="001")then
- STAR<=L0;
- elsif(clk5="010"and A="001")then
- STAR<=L1;
- elsif(clk5="011"and A="001")then
- STAR<=L2;
- elsif(clk5="100"and A="001")then
- STAR<=L3;
- elsif(clk5="101"and A="001")then
- STAR<=L4;
- elsif(clk6="01"and A="010")then
- STAR<=T0;
- elsif(clk6="10"and A="010")then
- STAR<=T1;
- else star<="11111111" ;
- end if;
- end process P2;
- end lyt;
- 失敗的時鐘
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity shizhong5091 is
- port ( clk:in std_logic;--時鐘信號
- led:out std_logic_vector(7 downto 0);--led燈
- led1_4:out std_logic_vector(3 downto 0));--控制七段譯碼管
- end shizhong5091;
- architecture lyt of shizhong5091 is
- signal clk1:std_logic_vector(25 downto 0);
- signal clk2:std_logic_vector(5 downto 0);
- signal clk3:std_logic_vector(3 downto 0);
- signal clk4:std_logic_vector(2 downto 0);
- signal clk5:std_logic_vector(3 downto 0);
- signal clk6:std_logic_vector(1 downto 0);
- signal A:std_logic_vector(2 downto 0);
- signal m0:std_logic_vector(7 downto 0);
- signal m1:std_logic_vector(7 downto 0);
- signal m2:std_logic_vector(7 downto 0);
- signal m3:std_logic_vector(7 downto 0);
- signal m4:std_logic_vector(7 downto 0);
- signal m5:std_logic_vector(7 downto 0);--保存十個不同數字的信號
- signal m6:std_logic_vector(7 downto 0);
- signal m7:std_logic_vector(7 downto 0);
- signal m8:std_logic_vector(7 downto 0);
- signal m9:std_logic_vector(7 downto 0);
- begin
- P1:process(clk)---控制七段顯示學號的進程
- begin
- if(clk'event and clk='1')then
- clk1<=clk1+1;
- if(clk1="10111110101111000010000000")then
- clk1<=(others=>'0'); ---時鐘控制
- if(clk3="1001")then
- clk3<=(others=>'0');
- if(clk4="100")then
- clk4<=(others=>'0');
- if(clk5="1011")then
- clk5<=(others=>'0');
- if(clk6="01")then
- clk6<=(others=>'0');
- else clk6<=clk6+1;
- end if;
- else clk5<=clk5+1;
- end if;
- else clk4<=clk4+1;
- end if;
- else clk3<=clk3+1;
- end if;
- end if;
- m0<="00000011";
- m1<="10011110";
- m2<="00100100";
- m3<="00001100";
- m4<="10011000";--儲存十個不同led數字
- m5<="01001000";
- m6<="01000000";
- m7<="00011110";
- m8<="00000000";
- m9<="00001000";
- if(clk3="0000")then
- led1_4<="1110";
- led<=m0;
- end if ;
- if(clk3="0001")then
- led1_4<="1110";
- led<=m1;
- end if ;
- if(clk3="0010")then
- led1_4<="1110";
- led<=m2;
- end if ;
- if(clk3="0011")then
- led1_4<="1110";
- led<=m3;
- end if ;
- if(clk3="0100")then
- led1_4<="1110";
- led<=m4;
- end if ;
- if(clk3="0101")then
- led1_4<="1110";
- led<=m5;
- end if ;
- if(clk3="0110")then
- led1_4<="1110";
- led<=m6;
- end if ;
- if(clk3="0111")then
- led1_4<="1110";
- led<=m7;
- end if ;
- if(clk3="1000")then
- led1_4<="1110";
- led<=m8;
- end if ;
- if(clk3="1001")then
- led1_4<="1110";
- led<=m9;
- end if ;
- if(clk4="000")then
- led1_4<="1101";
- led<=m0;
- end if ;
- if(clk4="001")then
- led1_4<="1110";
- led<=m1;
- end if ;
- if(clk4="010")then
- led1_4<="1101";
- led<=m2;
- end if ;
- if(clk4="011")then
- led1_4<="1101";
- led<=m3;
- end if ;
- if(clk4="100")then
- led1_4<="1101";
- led<=m4;
- end if ;
- if(clk4="101")then
- led1_4<="1101";
- led<=m5;
- end if ;
- if(clk5="0000")then
- led1_4<="1011";
- led<=m0;
- end if ;
- if(clk5="0001")then
- led1_4<="1011";
- led<=m1;
- end if ;
- if(clk5="0010")then
- led1_4<="1011";
- led<=m2;
- end if ;
- if(clk3="0011")then
- led1_4<="1011";
- led<=m3;
- end if ;
- if(clk5="0100")then
- led1_4<="1011";
- led<=m4;
- end if ;
- if(clk5="0101")then
- led1_4<="1011";
- led<=m5;
- end if ;
- if(clk5="0110")then
- led1_4<="1011";
- led<=m6;
- end if ;
- if(clk5="0111")then
- led1_4<="1011";
- led<=m7;
- end if ;
- if(clk5="1000")then
- led1_4<="1011";
- led<=m8;
- end if ;
- if(clk5="1001")then
- led1_4<="1011";
- led<=m9;
- end if ;
- if(clk5="1010")then
- led1_4<="1011";
- led<=m0;
- end if ;
- if(clk5="1011")then
- led1_4<="1011";
- led<=m1;
- end if ;
- if(clk6="00")then
- led1_4<="0111";
- led<=m0;
- end if ;
- if(clk6="01")then
- led1_4<="0111";
- led<=m1;
- end if ;
- end if;
- end process P1;
- end lyt;
復制代碼
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eda代碼.docx
2019-3-25 18:59 上傳
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