cordic算法詳細Verilog的代碼

ID:478137 · 發表于 2019-2-19 15:51

cordic算法的詳細代碼，包括tb代碼

源程序如下:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// Design Name:
// Module Name: Cordic
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Cordic(clk, phi, cos, sin);
parameter W = 10,W_Z = 11;
parameter PIPELINE=10;
input clk;
input [W_Z-1:0] phi;
output[W-1:0] cos,sin;
reg [W-1:0] cos,sin;
reg [W-1:0] x[10:0],y[10:0];
reg [W_Z-1:0] z[9:0];
reg sign[PIPELINE:0];
integer i;
always @(posedge clk)
begin
x[0] <= 10'h137; // 修正CORDIC算法的比例因子，An的倒數
y[0] <= 10'h00;
z[0] <= phi;
// 旋轉45度
if(z[0][W_Z-1]) begin
x[1] <= x[0] + y[0];
y[1] <= y[0] - x[0];
z[1] <= z[0] + 11'h192;
end
else begin
x[1] <= x[0] - y[0];
y[1] <= y[0] + x[0];
z[1] <= z[0] - 11'h192;
end
// 旋轉26.57度
if(z[1][W_Z-1]) begin
x[2] <= x[1] + {{1{y[1][W-1]}}, y[1][W-1:1]};
y[2] <= y[1] - {{1{x[1][W-1]}}, x[1][W-1:1]};
z[2] <= z[1] + 11'hF1;
end
else begin
x[2] <= x[1] - {{1{y[1][W-1]}}, y[1][W-1:1]};
y[2] <= y[1] + {{1{x[1][W-1]}}, x[1][W-1:1]};
z[2] <= z[1] - 11'hF1;
end
// 旋轉14.04度
if(z[2][W_Z-1]) begin
x[3] <= x[2] + {{2{y[2][W-1]}}, y[2][W-1:2]};
y[3] <= y[2] - {{2{x[2][W-1]}}, x[2][W-1:2]};
z[3] <= z[2] + 11'h80;
end
else begin
x[3] <= x[2] - {{2{y[2][W-1]}}, y[2][W-1:2]};
y[3] <= y[2] + {{2{x[2][W-1]}}, x[2][W-1:2]};
z[3] <= z[2] - 11'h80;
end
// 旋轉7.13度
if(z[3][W_Z-1]) begin
x[4] <= x[3] + {{3{y[3][W-1]}}, y[3][W-1:3]};
y[4] <= y[3] - {{3{x[3][W-1]}}, x[3][W-1:3]};
z[4] <= z[3] + 11'h40;
end
else begin
x[4] <= x[3] - {{3{y[3][W-1]}}, y[3][W-1:3]};
y[4] <= y[3] + {{3{x[3][W-1]}}, x[3][W-1:3]};
z[4] <= z[3] - 11'h40;
end
// 旋轉3.58度
if(z[4][W_Z-1]) begin
x[5] <= x[4] + {{4{y[4][W-1]}}, y[4][W-1:4]};
y[5] <= y[4] - {{4{x[4][W-1]}}, x[4][W-1:4]};
z[5] <= z[4] + 11'h20;
end
else begin
x[5] <= x[4] - {{4{y[4][W-1]}}, y[4][W-1:4]};
y[5] <= y[4] + {{4{x[4][W-1]}}, x[4][W-1:4]};
z[5] <= z[4] - 11'h20;
end
// 旋轉1.79度
if(z[5][W_Z-1]) begin
x[6] <= x[5] + {{5{y[5][W-1]}}, y[5][W-1:5]};
y[6] <= y[5] - {{5{x[5][W-1]}}, x[5][W-1:5]};
z[6] <= z[5] + 11'h10;
end
else begin
x[6] <= x[5] - {{5{y[5][W-1]}}, y[5][W-1:5]};
y[6] <= y[5] + {{5{x[5][W-1]}}, x[5][W-1:5]};
z[6] <= z[5] - 11'h10;
end
// 旋轉0.90度
if(z[6][W_Z-1]) begin
x[7] <= x[6] + {{6{y[6][W-1]}}, y[6][W-1:6]};
y[7] <= y[6] - {{6{x[6][W-1]}}, x[6][W-1:6]};
z[7] <= z[6] + 11'h8;
end
else begin
x[7] <= x[6] - {{6{y[6][W-1]}}, y[6][W-1:6]};
y[7] <= y[6] + {{6{x[6][W-1]}}, x[6][W-1:6]};
z[7] <= z[6] - 11'h8;
end
// 旋轉0.45度
if(z[7][W_Z-1]) begin
x[8] <= x[7] + {{7{y[7][W-1]}}, y[7][W-1:7]};
y[8] <= y[7] - {{7{x[7][W-1]}}, x[7][W-1:7]};
z[8] <= z[7] + 11'h4;
end
else begin
x[8] <= x[7] - {{7{y[7][W-1]}}, y[7][W-1:7]};
y[8] <= y[7] + {{7{x[7][W-1]}}, x[7][W-1:7]};
z[8] <= z[7] - 11'h4;
end
// 旋轉0.22度
if(z[8][W_Z-1]) begin
x[9] <= x[8] + {{8{y[8][W-1]}}, y[8][W-1:8]};
y[9] <= y[8] - {{8{x[8][W-1]}}, x[8][W-1:8]};
z[9] <= z[8] + 11'h2;
end
else begin
x[9] <= x[8] - {{8{y[8][W-1]}}, y[8][W-1:8]};
y[9] <= y[8] + {{8{x[8][W-1]}}, x[8][W-1:8]};
z[9] <= z[8] - 11'h2;
end
// 旋轉0.11度
if(z[9][W_Z-1])
begin
x[10] <= x[9] + {{9{y[9][W-1]}}, y[9][W-1:9]};
y[10] <= y[9] - {{9{x[9][W-1]}}, x[9][W-1:9]};
// z[10] <= z[9] + 11'h1;
end
else begin
x[10] <= x[9] - {{9{y[9][W-1]}}, y[9][W-1:9]};
y[10] <= y[9] + {{9{x[9][W-1]}}, x[9][W-1:9]};
// z[10] <= z[9] - 11'h1;
end
cos <= x[10][9]?~x[10]:x[10];
sin <= sign[PIPELINE]? ~(y[10][9]?~y[10]:y[10]) + 1 : y[10][9]?~y[10]:y[10];
end
always @(posedge clk)
begin
for(i=0;i<PIPELINE;i=i+1)
sign[i+1] <= sign[i];
sign[0] <= phi[W_Z-1];
end
endmodule

復制代碼

所有資料51hei提供下載:

7660161.zip (1.36 MB, 下載次數: 17)

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cordic算法詳細Verilog的代碼

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