library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity stopwatch is
port(
mode:in std_logic_vector(1 downto 0);
clk:in std_logic;-----------100hz 精確度位0.01s
start:in std_logic;--step_up
clr:in std_logic;
d_6,d_7,d_8,d_9:out std_logic_vector(3 downto 0)
);
end stopwatch;
architecture struct of stopwatch is
component count_10_d_0 is
port(
mode:in std_logic_vector(1 downto 0);
clk1,clear,start:in std_logic;
bcd_out:out std_logic_vector(3 downto 0);
cout:buffer std_logic);
end component;
component count_10_d_1 is
port( clk2,clear:in std_logic;
bcd_out:out std_logic_vector(3 downto 0);
cout:buffer std_logic);
end component;
component count_10_d_2 is
port( clk3,clear:in std_logic;
bcd_out:out std_logic_vector(3 downto 0);
cout:buffer std_logic);
end component;
component count_10_d_3 is
port( clk4,clear:in std_logic;
bcd_out:out std_logic_vector(3 downto 0);
cout:buffer std_logic);
end component;
signal clk1,clk2,clk3,cout:std_logic;
begin
u31:count_10_d_0 port map(mode,clk,clr,start,d_6,clk1);
u32:count_10_d_1 port map(clk1,clr,d_7,clk2);
u33:count_10_d_2 port map(clk2,clr,d_8,clk3);
u34:count_10_d_3 port map(clk3,clr,d_9,cout);
end architecture struct;
3.3秒表底層文件3.3.1、十進(jìn)制計時器（4個計數(shù)器級聯(lián)）library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_10_d_0 is
port(
mode:in std_logic_vector(1 downto 0);
clk1,clear,start:in std_logic;
bcd_out:out std_logic_vector(3 downto 0);
cout:buffer std_logic
);
end entity count_10_d_0;
architecture behavioral of count_10_d_0 is
signal temp:std_logic_vector(3 downto 0);
signal start_state:std_logic:='1';
begin
process(start)
begin
if(start'event and start='1')then
if(mode="10")then
start_state<=not start_state;
else
start_state<='1';
end if;
else start_state<=start_state;
end if;
end process;
process(clk1,clear)is
begin
if(clear='1')then
temp<="0000";cout<='0';
elsif(clk1'event and clk1='1')then
if(start_state='0')then
if(temp="1001")then
temp<="0000";cout<='1';
else
temp<=temp+1;cout<='0';
end if;
else
temp<=temp;
end if;
end if;
bcd_out<=temp;
end process;
end architecture behavioral;
4、定時鬧鐘4.1、鬧鐘頂層原理圖
4.2、鬧鐘頂層程序library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timer is
port(
clk:in std_logic;
mode:in std_logic_vector(1 downto 0);
clk_1hz:in std_logic;
clk_2hz:in std_logic;
flag2:in std_logic_vector(2 downto 0);
step_up:in std_logic;
clr:in std_logic;
d_10,d_11,d_12,d_13:out std_logic_vector(3 downto 0);
led:out std_logic;
alarm_on:in std_logic;
t_now5,t_now4,t_now3,t_now2:in std_logic_vector(3 downto 0)
);
end entity;
architecture struct of timer is
component xuanze_mode_4_1 is
port(
clk:in std_logic;
in2,in3,in4,in5:in std_logic;
step_up:in std_logic;
flag2:in std_logic_vector(2 downto 0);
co2,co3,co4,co5:out std_logic
);
end component;
component time_set is
port (
clk:in std_logic;
mode:in std_logic_vector(1 downto 0);
flag2:in std_logic_vector(2 downto 0);
clk1,clk2,clk3,clk4:in std_logic;
clear:in std_logic;
step_up:in std_logic;
d_10,d_11,d_12,d_13:out std_logic_vector(3 downto 0);
cout4:buffer std_logic;
alarm_on:in std_logic;
t_now5,t_now4,t_now3,t_now2:in std_logic_vector(3 downto 0)
);
end component;
component alarm is
port(
clk:in std_logic;
c_in:in std_logic;
c_out:out std_logic
);
end component;
signal cout1,cout2,cout3,cout4,clk1,clk2,clk3,clk4:std_logic;
begin
u40:xuanze_mode_4_1 port map(clk,clk_1hz,cout1,cout2,cout3,step_up,flag2,clk1,clk2,clk3,clk4);
u41:time_set port map(clk,mode,flag2,clk1,clk2,clk3,clk4,clr,step_up,d_10,d_11,d_12,d_13,cout4,alarm_on,t_now5,t_now4,t_now3,t_now2);
u42:alarm port map(clk_2hz,cout4,led);
end struct;
4.3、鬧鐘底層文件4.3.1、調(diào)整位選擇library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xuanze_mode_4_1 is
port(
clk:in std_logic;
in2,in3,in4,in5:in std_logic;
step_up:in std_logic;
flag2:in std_logic_vector(2 downto 0);
co2,co3,co4,co5:out std_logic
);
end xuanze_mode_4_1;
architecture behav of xuanze_mode_4_1 is
begin
process(clk,flag2,in2,in3,in4,in5,step_up)
begin
case flag2 is
when "000" => co2<=in2;
co3<=in3;
co4<=in4;
co5<=in5;
when "001" => co2<=step_up;
co3<=in3;
co4<=in4;
co5<=in5;
when "010" => co3<=step_up;
when "011" => co4<=step_up;
when "100" => co5<=step_up;
when others => null;
end case;
end process;
end behav;
4.3.2、時間設(shè)定library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_set is
port(
clk:in std_logic;
mode:in std_logic_vector(1 downto 0);
flag2:in std_logic_vector(2 downto 0);
clk1,clk2,clk3,clk4:in std_logic;
clear:in std_logic;
step_up:in std_logic;
d_10,d_11,d_12,d_13:out std_logic_vector(3 downto 0);
cout4:buffer std_logic;
alarm_on:in std_logic;
t_now5,t_now4,t_now3,t_now2:in std_logic_vector(3 downto 0)
);
end time_set;
architecture behav of time_set is
signal temp1,temp2,temp3,temp4:std_logic_vector(3 downto 0);
signal start_state:std_logic:='1';
begin
process(clk,cout4)
begin
if(clk'event and clk='1')then
if(alarm_on='0')then
----目前時間和設(shè)定的時間對比
if(t_now5=temp4 and t_now4=temp3 and t_now3=temp2 and t_now2=temp1)then
cout4<='1';
else
cout4<='0';
end if;
else
cout4<='0';
end if;
end if;
end process;
process(clk1,clear)is
begin
if(clear='1')then
temp1<="0000";
elsif(clk1'event and clk1='1')then--有脈沖信號 進(jìn)行數(shù)字調(diào)整 +1
if(flag2/="000")then
if(temp1="1001")then
temp1<="0000";
else
temp1<=temp1+1;
end if;
end if;
end if;
d_10<=temp1;
end process;
process(clk2,clear)is
begin
if(clear='1')then
temp2<="0000";
elsif(clk2'event and clk2='1')then
if(flag2/="000")then
if(temp2="1001")then
temp2<="0000";
else
temp2<=temp2+1;
end if;
end if;
end if;
d_11<=temp2;
end process;
process(clk3,clear)is
begin
if(clear='1')then
temp3<="0000";
elsif(clk3'event and clk3='1')then
if(flag2/="000")then
if(temp3="1001")then
temp3<="0000";
else
temp3<=temp3+1;
end if;
end if;
end if;
d_12<=temp3;
end process;
process(clk4,clear)is
begin
if(clear='1')then
temp4<="0000";
elsif(clk4'event and clk4='1')then
if(flag2/="000")then
if(temp4="1001")then
temp4<="0000";
else
temp4<=temp4+1;
end if;
end if;
end if;
d_13<=temp4;
end process;
end behav;
4.3.3、鬧鈴library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alarm is
port(
clk:in std_logic;
c_in:in std_logic;
c_out:out std_logic--led
);
end entity;
architecture behav of alarm is
signal alarm_state:std_logic:='0';
begin
process(c_in,clk)
begin
if(c_in='1')then
if(clk='1')then
c_out<='1';
else
c_out<='0';
end if;
else
c_out<='0';
end if;
end process;
end behav;
5、按鍵消抖5.1、按鍵消抖原理圖
5.2、按鍵消抖底層程序library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key is
port(
clk:in std_logic;
mode,set,step_up,ok,clr:in std_logic;
mode_out,set_out,step_up_out,ok_out,clr_out:out std_logic
);
end key;
architecture behav of key is
begin
process(clk,mode,set,step_up,ok,clr)
variable count1,count2,count3,count4,count5:integer range 0 to 1000000; --20ms延時消抖
begin
if rising_edge(clk) then
if mode='0' then
if count1<1000000 then
count1:=count1+1;
else
count1:=count1;
end if;
if count1<=999999 then
mode_out<='1';
else
mode_out<='0';
end if;
else count1:=0;
end if;
if set='0' then
if count2<1000000 then
count2:=count2+1;
else
count2:=count2;
end if;
if count2<=999999 then
set_out<='1';
else
set_out<='0';
end if;
else count2:=0;
end if;
if step_up='0' then
if count3<1000000 then
count3:=count3+1;
else
count3:=count3;
end if;
if count3<=999999 then
step_up_out<='1';
else
step_up_out<='0';
end if;
else count3:=0;
end if;
if ok='0' then
if count4<1000000 then
count4:=count4+1;
else
count4:=count4;
end if;
if count4<=999999 then
ok_out<='1';
else
ok_out<='0';
end if;
else count4:=0;
end if;
if clr='0' then
if count5<1000000 then
count5:=count5+1;
else
count5:=count5;
end if;
if count5<=999999 then
clr_out<='1';
else
clr_out<='0';
end if;
else count5:=0;
end if;
end if;
end process ;
end behav;
6、按鍵處理部分
6.1按鍵處理原理圖
6.2按鍵處理底層程序1 / 2
工程框架及頂層原理圖
2.3.2、秒——60進(jìn)制芯片
library ieee;
2.3.4、時——12/24進(jìn)制芯片
3.1、秒表頂層、底層原理圖
7.1、原理圖
8.1、原理圖
9、數(shù)碼管譯碼器9.1、原理圖
2、時鐘暫停及運行
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