我用VHDL語言實現的簡單CPU設計

ID:280277 · 發表于 2018-7-14 18:20

使用VHDL語言編寫的一個課程設計，寫了一個簡單CPU，包含通用寄存器，PC寄存器,ALU等等,供大家參考

單片機源程序如下:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package packexp is
function calculator(ch : std_logic_vector(2 downto 0);
da,db :std_logic_vector(7 downto 0))
return std_logic_vector;
end;
package body packexp is
function calculator(ch : std_logic_vector(2 downto 0); da,db : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
case(ch) is
when "001" =>
return ('0' & (da and db));
when "010" =>
return ('0' & (da or db));
when "011" =>
return ('0' & (da xor db));
when "100" =>
return ('0' & da) + ('0' & db);
when "101" =>
return ('0' & da(6 downto 0) & '0');
when "110" =>
return ('0' & '0' & da(7 downto 1));
when "111" =>
return ('0' & da(7) & da(7 downto 1));
when others =>
return ("000000000");
end case;
end function calculator;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.packexp.all;
entity ALU is
port(clk : in std_logic;
mode : in std_logic_vector(1 downto 0);
S : in std_logic_vector(2 downto 0);
Cin : in std_logic;
D : in std_logic_vector(7 downto 0);
Cout : out std_logic;
dataout : out std_logic_vector(7 downto 0));
end entity ALU;
architecture mainpart of ALU is
begin
process(clk)
variable A : std_logic_vector(7 downto 0) := (others => '0');
variable B : std_logic_vector(7 downto 0) := (others => '0');
variable dataa : std_logic_vector(7 downto 0) := (others => '0');
variable datab : std_logic_vector(7 downto 0) := (others => '0');
variable result : std_logic_vector(8 downto 0) := (others => '0');
begin
if(clk'event and clk = '1')
then
if(S = "000")
then
A := (others => '0');
B := (others => '0');
result := (others => '0');
dataout <= result(7 downto 0);
else
case(mode) is
when "00" =>
A := D;
dataout <= A;
when "01" =>
B := D;
dataout <= B;
when "11" | "10" =>
dataa := A;
datab := B;
result := calculator(S,dataa,datab);
if(S = "100")
then
result := result + ("00000000" & Cin);
Cout <= result(8);
else
Cout <= '0';
end if;
dataout <= result(7 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
end mainpart;

復制代碼

所有資料51hei提供下載:

9.ALU.rar (5.49 MB, 下載次數: 55)

ID:258507 · 發表于 2019-2-28 17:54

bucuo，支持一下。正好學習了VHDL，在做畢設

ID:517723 · 發表于 2019-4-21 13:17

我最近有個大作業也在做這個，但是管腳映射除了奇怪的問題。
file3:MBR port map(CLK=>CLK,RST=>RST,control_signal=>control_signal,from_memory=>spo_ram,from_ACC=>ACC_L,to_memory=>to_memory,MBR_out=>MBR_out,wren=>wren);
file12:RAM1 port map(a=>address(4 downto 0),d=>MBR_out,clk=>CLK,we=>wren,spo=>spo_ram);
其中from_memory是in 變量，spo是out變量，spo_ram是頂層文件的臨時變量。現在仿真以后，spo和spo_ram都成功地讀到了ram里面第一行的數據，但是from_mpmery就是沒有這個變量，還是一個空值，使得后續所有的變量全部沒用了。這到底是什么問題？

ID:392858 · 發表于 2019-12-25 16:48

支持下

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我用VHDL語言實現的簡單CPU設計