基于verilog的流水燈程序

ID:322446 · 發表于 2018-5-4 22:44

基于verilog的流水燈程序

//===========================================================================
// File Name : FLOW_LED
// Module Name : FLOW_LED
// Description : This is a led control module,which it control the led flow.
// Project :
// Belong to :
// Author :
// Date :
// Rev. :
//---------------------------------------------------------------------------
// Rev. Date Description
//---------------------------------------------------------------------------
//===========================================================================
`define UD #1
module FLOW_LED
(
//Input ports.
SYSCLK,
RST_B,
//Output ports.
LED
);
//===========================================================================
//Input and output declaration
//===========================================================================
input SYSCLK; //System clock, 50MHz.
input RST_B; //Global reset, low active.
output[7:0] LED;
//===========================================================================
//Wire and reg declaration
//===========================================================================
wire SYSCLK;
wire RST_B;
reg[7:0] LED;
//===========================================================================
//Wire and reg in the module
//===========================================================================
reg[7:0] LED_N;
reg[24:0] TIME_CNT;
reg[24:0] TIME_CNT_N;
//===========================================================================
//Logic
//===========================================================================
parameter T_NUM = 25'h17D7840;//25'h17D7840
always @ (posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
TIME_CNT <= 25'h0;
else
TIME_CNT <= TIME_CNT_N;
end
always @ ( * )
begin
if(TIME_CNT == T_NUM)
TIME_CNT_N = 25'h0;
else
TIME_CNT_N = TIME_CNT + 25'h1;
end
always @ (posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
LED <= 8'b1111_1110;
else
LED <= LED_N;
end
always @ (*)
begin 0000000
if((TIME_CNT == T_NUM)&&(LED == 8'b0))
LED_N = 8'b1111_1110;
else if(TIME_CNT == T_NUM)
LED_N = (LED << 1);
else
LED_N = LED;
end
endmodule

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基于verilog的流水燈程序