VHDL直流電機控制系統課設總原理圖與源程序部分

ID:263449 · 發表于 2018-1-17 02:52

附錄

課設總原理圖（附件中有清晰的圖片下載）：

VHDL直流電機控制系統課設頂層文件：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FX IS
PORT
(
C0 : IN STD_LOGIC;
K2 : IN STD_LOGIC;
K1 : IN STD_LOGIC;
C1 : IN STD_LOGIC;
KIN : IN STD_LOGIC;
clk1 : IN STD_LOGIC;
M0 : OUT STD_LOGIC;
M1 : OUT STD_LOGIC;
M : OUT STD_LOGIC;
CLK : OUT STD_LOGIC;
LK : OUT STD_LOGIC;
KOUT : OUT STD_LOGIC;
ADR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CIN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FX;
ARCHITECTURE bdf_type OF FX IS
COMPONENT cnt8b
PORT(CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT erzp
PORT(CLK : IN STD_LOGIC;
KIN : IN STD_LOGIC;
KOUT : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tf_ctrl
PORT(CLK1 : IN STD_LOGIC;
CNT_EN : OUT STD_LOGIC;
CLR : OUT STD_LOGIC;
LOCK : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cnt10d
PORT(CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
ENABL : IN STD_LOGIC;
COUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT lock8
PORT(LK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT cnt4b
PORT(CLK : IN STD_LOGIC;
CIN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT squ1
PORT(ADR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
OT : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT slt
PORT(SL : IN STD_LOGIC;
M : IN STD_LOGIC;
m0 : OUT STD_LOGIC;
m1 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT decl7s
PORT(A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
M <= SYNTHESIZED_WIRE_9;
CLK <= SYNTHESIZED_WIRE_6;
LK <= SYNTHESIZED_WIRE_4;
KOUT <= SYNTHESIZED_WIRE_1;
ADR <= SYNTHESIZED_WIRE_7;
CIN <= SYNTHESIZED_WIRE_8;
b2v_inst : cnt8b
PORT MAP(CLK => C0,
DOUT => SYNTHESIZED_WIRE_7);
b2v_inst1 : erzp
PORT MAP(CLK => C0,
KIN => SYNTHESIZED_WIRE_0,
KOUT => SYNTHESIZED_WIRE_6);
b2v_inst11 : tf_ctrl
PORT MAP(CLK1 => clk1,
CNT_EN => SYNTHESIZED_WIRE_3,
CLR => SYNTHESIZED_WIRE_2,
LOCK => SYNTHESIZED_WIRE_4);
b2v_inst12 : cnt10d
PORT MAP(CLK => SYNTHESIZED_WIRE_1,
CLR => SYNTHESIZED_WIRE_2,
ENABL => SYNTHESIZED_WIRE_3,
COUT => SYNTHESIZED_WIRE_5,
DOUT1 => DOUT1,
DOUT2 => DOUT);
b2v_inst13 : lock8
PORT MAP(LK => SYNTHESIZED_WIRE_4,
D => SYNTHESIZED_WIRE_5,
Q => Q);
b2v_inst2 : cnt4b
PORT MAP(CLK => SYNTHESIZED_WIRE_6,
CIN => SYNTHESIZED_WIRE_8,
DOUT => SYNTHESIZED_WIRE_11);
b2v_inst3 : squ1
PORT MAP(ADR => SYNTHESIZED_WIRE_7,
CIN => SYNTHESIZED_WIRE_8,
OT => SYNTHESIZED_WIRE_10);
b2v_inst4 : slt
PORT MAP(SL => K1,
M => SYNTHESIZED_WIRE_9,
m0 => M0,
m1 => M1);
SYNTHESIZED_WIRE_0 <= NOT(K2);
SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_10);
b2v_inst7 : decl7s
PORT MAP(A => SYNTHESIZED_WIRE_11,
LED7S => LED);
b2v_inst8 : erzp
PORT MAP(CLK => C1,
KIN => KIN,
KOUT => SYNTHESIZED_WIRE_1);
END bdf_type;
消抖模塊：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ERZP IS
PORT(CLK,KIN : IN STD_LOGIC;
KOUT : OUT STD_LOGIC );
END;
ARCHITECTURE BHV OF ERZP IS
SIGNAL KL,KH : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,KIN,KL,KH ) BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF(KIN='0') THEN KL<=KL+1;
ELSE KL<="0000"; END IF;
IF(KIN='1') THEN KH<=KH+1;
ELSE KH<="0000"; END IF;
IF(KH>"0101") THEN KOUT<='1';
ELSIF (KL>"0101") THEN KOUT<='0';
END IF; END IF;
END PROCESS;
END;
頻率控制模塊：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TF_CTRL IS
PORT (CLK1 : IN STD_LOGIC; -- 1Hz
CNT_EN : OUT STD_LOGIC; -- 計數器時鐘使能
CLR : OUT STD_LOGIC; -- 計數器清零
LOCK : OUT STD_LOGIC ); -- 輸出鎖存信號
END TF_CTRL;
ARCHITECTURE behav OF TF_CTRL IS
SIGNAL Div2CLK : STD_LOGIC;
BEGIN
PROCESS( CLK1 )
BEGIN
IF CLK1'EVENT AND CLK1 = '1' THEN
Div2CLK <= NOT Div2CLK;
END IF;
END PROCESS;
PROCESS (CLK1, Div2CLK)
BEGIN
IF CLK1='0' AND Div2CLK='0' THEN CLR<='1';-- 產生計數器清零信號
ELSE CLR <= '0'; END IF;
END PROCESS;
LOCK <= NOT Div2CLK; CNT_EN <= Div2CLK;
END behav;
頻率計數模塊：
LIBRARY IEEE; --8位計數器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10D IS
PORT (CLK : IN STD_LOGIC; -- 時鐘信號
CLR : IN STD_LOGIC; -- 清零信號
ENABL : IN STD_LOGIC; -- 計數使能信號
COUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); -- 計數結果
END CNT10D;
ARCHITECTURE behav OF CNT10D IS
SIGNAL CQ2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CQ3 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK, CLR, ENABL)
BEGIN
IF CLR = '1' THEN CQ2 <= (OTHERS=>'0'); CQ3 <= (OTHERS=>'0'); -- 清零
ELSIF CLK'EVENT AND CLK = '1' THEN
IF ENABL = '1' THEN IF CQ2>8 THEN CQ2(3 DOWNTO 0)<="0000"; CQ3<=CQ3+1;
ELSE CQ2 <=CQ2+1;
END IF;
END IF;
END IF;
END PROCESS;
COUT <= CQ3&CQ2;
DOUT1 <=CQ2;
DOUT2 <=CQ3;
END behav;
8位鎖存模塊：
LIBRARY IEEE; --8位鎖存器
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LOCK8 IS
PORT ( LK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
LEDB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END LOCK8;
ARCHITECTURE behav OF LOCK8 IS
BEGIN
PROCESS(LK, D)
BEGIN
IF LK'EVENT AND LK = '1' THEN LEDA <= D(7 DOWNTO 4); LEDB <= D(3 DOWNTO 0);
END IF;
END PROCESS;
END behav;
8位計數器模塊：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT8B IS
PORT (CLK : IN STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END CNT8B;
ARCHITECTURE BHV OF CNT8B IS
BEGIN
PROCESS(CLK)
VARIABLE CQ : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF CQ<255 THEN --
CQ := CQ + 1 ;
ELSE CQ := (OTHERS=>'0') ;
END IF;
END IF;
DOUT <= CQ;
END PROCESS;
END BHV;
4位計數器模塊：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4B IS
PORT (CLK : IN STD_LOGIC;
CIN: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END CNT4B;
ARCHITECTURE BHV OF CNT4B IS
SIGNAL CQ1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
VARIABLE CQ : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
CQ1 <="1111";
IF CLK'EVENT AND CLK = '1' THEN
IF CQ<15 THEN
CQ := CQ + 1 ;
ELSE CQ := (OTHERS=>'0') ;
END IF;
END IF;
DOUT <=CQ(3 DOWNTO 0);
CIN <=CQ&CQ1;
END PROCESS;
END BHV;
PWM信號產生模塊：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SQU1 IS
PORT ( CIN,ADR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
OT : OUT STD_LOGIC );
END SQU1;
ARCHITECTURE BHV OF SQU1 IS
BEGIN
PROCESS(CIN) BEGIN
IF (ADR<CIN) THEN OT<='0';
ELSE OT<='1'; END IF;
END PROCESS;
END BHV;
正反轉模塊:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY SLT IS
PORT (SL, M, K : IN STD_LOGIC;
m0, m1: OUT STD_LOGIC );
END SLT;
ARCHITECTURE BHV OF SLT IS
TYPE FSM_ST IS (S0,S1);
SIGNAL c_st, next_state: FSM_ST :=S0;
BEGIN
REG : PROCESS (SL)
BEGIN
IF SL='1'AND SL'EVENT THEN c_st <= next_state;
END IF;
END PROCESS REG ;
COM : PROCESS (c_st, M) BEGIN
IF K='1' THEN m0 <='0'; m1 <='0';
ELSE
CASE c_st IS
WHEN S0 => m0 <= M; m1 <='0'; next_state <= S1;
WHEN S1 => m1 <= M; m0 <='0'; next_state <= S0;
END CASE;
END IF;
END PROCESS;
END BHV;
分頻模塊：實際測試時沒有用，因為開發箱直接有1Hz的時鐘。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT IS
PORT(CLOCK : IN STD_LOGIC ;COUT : OUT STD_LOGIC);
END ;
ARCHITECTURE bhv OF CNT IS
SIGNAL C1,C2 : STD_LOGIC_VECTOR(8 DOWNTO 0) ;
SIGNAL M1,M2 : STD_LOGIC ;
BEGIN
PROCESS(CLOCK,C1) BEGIN
IF RISING_EDGE(CLOCK) THEN
IF (C1="111111111") THEN C1<="000000000"; ELSE C1<=C1+1; END IF;
IF (C1="000000001") THEN M1<=NOT M1; ELSIF (C1="100000000") THEN M1<=NOT M1;
END IF;END IF;
END PROCESS;
PROCESS (CLOCK,C2) BEGIN
IF FALLING_EDGE(CLOCK) THEN
IF(C2="111111111") THEN C2<="000000000"; ELSE C2<=C2+1;END IF;
IF(C2="000000001") THEN M2<=NOT M2 ; ELSIF (C2="100000000") THEN M2<=NOT M2;
END IF; END IF;
END PROCESS;
COUT<=M1 OR M2;
END bhv

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基于VHDL的直流電機控制系統程序.7z (42.82 KB, 下載次數: 71)

ID:263449 · 發表于 2018-1-17 02:55

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VHDL直流電機控制系統課設總原理圖與源程序部分