日志
ENA設(shè)計(jì)
--頂層實(shí)體元件設(shè)計(jì)模塊
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; --調(diào)用算術(shù)運(yùn)算符的重載函數(shù)的聲明
ENTITY ADDER_NB IS
GENERIC(S : INTEGER := 8); --參數(shù)傳遞說明語句，類屬參量S默認(rèn)為8，可直接修改
-- GENERIC(S : INTEGER := 16);
-- GENERIC(S : INTEGER := N); --N為任意正整數(shù)
PORT(A,B : IN STD_LOGIC_VECTOR(S-1 DOWNTO 0);
CIN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(S-1 DOWNTO 0);
COUT : OUT STD_LOGIC);
END ENTITY ADDER_NB;
ARCHITECTURE ONE OF ADDER_NB IS
SIGNAL DATA : STD_LOGIC_VECTOR(S DOWNTO 0); --定義信號變量DATA
SIGNAL BW : STD_LOGIC_VECTOR(S-1 DOWNTO 0); --定義變量BW，用來數(shù)據(jù)運(yùn)算補(bǔ)位
BEGIN
BW <= (OTHERS => '0');
DATA <= ('0' & A) + ('0' & B) + (BW & CIN );
DOUT <= DATA(S-1 DOWNTO 0);
COUT <= DATA(S);
END ARCHITECTURE ONE;
設(shè)計(jì)與仿真截圖如下：
設(shè)計(jì)與仿真截圖如下：
